Automated Circuit Optimization Using Boundary Lemmas
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current automated circuit design methods face limitations in optimizing and verifying digital circuit designs across hierarchical boundaries, leading to inefficiencies in synthesis transformation and equivalence checking, as optimizations are typically restricted within individual hierarchical blocks, limiting the scope of automated optimization and potentially resulting in false non-equivalence results.
Innovation Solution
The method involves automatically generating lemmas that specify range information for boundary nodes, allowing for optimization and equivalence checking across hierarchical boundaries while preserving the hierarchical structure, by propagating range information from output boundaries to input boundaries, and using these lemmas for both synthesis transformation and equivalence checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical blocks are individually optimized and verified, then verification complexity is reduced and hierarchical structure is preserved, but optimization scope is limited within blocks and cannot cross hierarchical boundaries
Solution Approach 1:
The patent introduces lemmas as intermediary elements that bridge hierarchical blocks. These lemmas capture the behavior of blocks at their boundaries and allow optimization to cross hierarchical boundaries while maintaining the hierarchical structure. The lemmas serve as mediators between individual blocks and the overall system, enabling verification of cross-boundary optimizations without flattening the hierarchy.
Solution Approach 2:
The patent implements nested verification where lemmas are embedded within hierarchical blocks, and equivalence checking is nested across multiple hierarchy levels. The verification process operates at both the block level and the system level simultaneously, with lemmas providing the interface between these nested verification layers.
2Adaptability or versatility
If the entire circuit is flattened for optimization, then optimization scope covers the whole circuit, but computation resources are exceeded and verification becomes infeasible
Solution Approach 1:
The patent segments the verification process into hierarchical blocks with lemmas at their boundaries. Instead of verifying the entire flattened circuit at once, the verification is divided into manageable block-level verifications using lemmas, and cross-boundary verifications using lemma equivalence. This segmentation reduces computation resource requirements while maintaining full-circuit optimization capability.
3Reliability
If manual user assertions are prescribed for equivalence checking, then false non-equivalence results are prevented, but design automation is reduced and manual effort increases
Solution Approach 1:
The patent implements self-service automation where the system automatically generates lemmas from hierarchical block definitions and automatically proves their equivalence. The lemmas are derived systematically from the block interfaces and behaviors, eliminating the need for manual user assertions. The equivalence checking process automatically uses these generated lemmas to prevent false non-equivalence results, maintaining both automation and reliability.
Data Source
AI summary
Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.