Circuit Resource Estimation for Programmable Logic Design
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Solution Overview
Problem
The complexity of capturing hardware system descriptions in synthesizable languages makes it time-consuming for designers to optimize circuit designs, particularly in programmable logic devices, due to limited feedback and correlation between source code and hardware, leading to difficulties in resource management and device selection.
Innovation Solution
A method that identifies intermediate circuit modules in a netlist, accesses a library of resource requirements, selects modules based on predetermined parameters, and generates estimates of resource requirements, displaying them as source code is entered to facilitate optimization and device selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If high-level languages are used to describe complex hardware systems, then the design cycle is compressed and time-to-market is shorter, but limited feedback and correlation between source code and hardware make it difficult to optimize designs
Solution Approach 1:
The patent implements feedback mechanisms by providing resource estimation information back to the designer during the high-level language design phase. The system analyzes the netlist generated from HLL code, estimates resource requirements, and presents this feedback to the designer, enabling iterative optimization without leaving the high-level design environment.
Solution Approach 2:
The patent introduces an intermediary estimation tool that bridges the gap between high-level language source code and hardware resource requirements. This intermediary system translates HLL code into netlists, performs resource estimation, and provides correlated feedback, maintaining the benefits of high-level design while adding hardware-aware optimization capabilities.
2Measurement precision
If implementation tools are run to determine resource requirements and device compatibility, then accurate information is obtained, but run times are significant requiring costly engineering time and causing delays
Solution Approach 1:
The patent applies preliminary action by performing resource estimation early in the design process, before full implementation tool runs are executed. The system provides preliminary resource requirement estimates based on netlist analysis, allowing designers to make informed decisions about device selection and design optimization before committing significant engineering time to full implementation.
Solution Approach 2:
The patent uses partial action by implementing a simplified resource estimation approach that analyzes netlists without requiring complete implementation tool execution. The system performs partial resource analysis on intermediate circuit modules and aggregates these estimates, providing sufficient information for early design decisions without the full computational overhead of complete implementation runs.
3Reliability
If full implementation is performed to determine device compatibility, then accurate device selection is possible, but design time and engineering resources are significantly consumed
Solution Approach 1:
The patent enables preliminary device compatibility assessment by estimating resource requirements early in the design process. Designers can preliminarily evaluate whether a device is suitable for their design based on estimated resource usage before committing to full implementation, improving productivity while maintaining the ability to make accurate device selections.
Solution Approach 2:
The patent applies partial action by performing simplified resource estimation on intermediate circuit modules rather than complete implementation. This partial analysis provides sufficient information for early device compatibility assessment and design optimization, accelerating the design process while maintaining reliability through iterative refinement.
Data Source
AI summary
A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.