Detecting Faulty Computer Hardware TRIZ Cases
- Multi-Core Processor Error Management via Core Swapping
A multi-core processor manages hardware errors by swapping spare cores for failing main cores without interrupting operating system execution.
- Cell Library Pin Utilization Analysis for Routing Reliability
A software tool calculates pin connection utilization metrics from placed layouts to identify potential routing failures in standard cell libraries.
- Compact Modeling Transistor Characteristics Using TCAD Physics
Physics-based compact models derive electrical parameters from technology computer-aided design simulations to capture device behavior.
- 2D OPC Model Using Scalable Test Patterns for IC Contour Accuracy
A two-dimensional optical proximity correction model generates reticle patterns using scalable test structures to match target contours.
- Circuit Resource Estimation for Programmable Logic Design
Analyzes intermediate modules via a library to resolve feedback gaps in programmable logic.
- Semiconductor Mask Design for White Bump Prevention
A failure analysis tool calculates solder bump stress radii to identify critical wiring areas on semiconductor chips.
- Bi-exponential Statistical Leakage Modeling for IC Yield
Bi-exponential statistical analysis characterizes leakage power across process parameters to resolve manufacturing yield loss from nanometer-scale variations.
- Parasitic Model Evaluation with Varying Accuracy Modes
Automated parasitic evaluation system supports simulation modes of varying accuracy for circuit design.
- RC Extraction Tool for Through-Semiconductor-Via Distance Measurement
An RC extraction tool determines distances between through-semiconductor-vias to model parasitic parameters accurately.
- Simulation Driver Context Stack for IP Execution
A simulation driver saves context information to a stack during execution on a workstation.
- Backplane Initiator Testing EMC Compatibility
A backplane initiator transmits control commands via SGPIO and SMBus interfaces to verify enclosure management controller functionality.
- Electronic Circuit Model Synthesis via Electromagnetic Data Apportionment
Apportions electromagnetic analysis data to configure candidate components, resolving iterative approximation bottlenecks that limit model precision.
- Debug Architecture for SoC with Shared Hub and Circular Buffers
A debug architecture streams peripheral data to separate stores via a shared hub.
- Trace Bandwidth Estimation for SoC CoreSight Architecture
Software program estimates trace bandwidth requirements using FIFO levels and overflow analysis.
- Touch Screen Test Apparatus Offloading Data Processing
A touch screen test apparatus converts collected information into a format recognizable by an intelligent device for external processing.
- Integrated Circuit Control Points for OPC Defect Detection
Control points with stored attributes guide integrated circuit wafer design, reducing optical proximity correction cycles.
- Equivalent Waveform Model for Static Timing Analysis
An equivalent waveform model uses analog simulation to generate discrete templates for complex input signals.
- Statistical Timing Analysis for Latch Circuits with Feedback Loops
Iterative statistical timing analysis updates signal arrival and departure times to resolve computational complexity in feedback loop circuits.
- PCIe Error Injection Platform for Server RAS Testing
A software-based PCIe error injection platform automates correctable and non-correctable fault insertion for hardware validation.
- RC Tech File Generation via Pattern-Based Capacitance Extraction
Pattern-based capacitance extraction assembles reusable technology files, eliminating redundant field solver calculations across varying technology nodes.
- Deadlock Detection in Integrated Circuit Power Nodes
A deadlock detection method retrieves power node inputs and starting orders to identify circuit path conflicts.
- Multi-Level IC Debugging Synchronization
Correlates signals between RTL and gate levels to eliminate manual translation bottlenecks during chip design debugging.
- Multi-Voltage Metal Line Routing via Local Quality Spacing
A routing program assigns distinct spacing attributes to voltage-specific layer types on a single metal plane.
- Heterogeneous Rad-Hard Computing System with Dual Processor Segmentation
Segmenting processing into rad-hard and conventional units mitigates radiation-induced errors without increasing power requirements.
- Post-Singulation Wiring Layout Modification for Passive Component Tolerance
A processing circuit determines electrical connections based on measured passive component values to adjust capacitance or inductance.
- Signal Tracing Across Boards and Chips for Failure Analysis
A computer-implemented method traces signal paths across boards and chips to identify defects in electronic circuitry.