Debug Architecture for SoC with Shared Hub and Circular Buffers
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Solution Overview
Problem
Debugging of System-on-Chip (SoC) devices is hindered by the integration of multiple core devices onto a single chip, limiting external debugging tools' ability to find and solve bugs within the required timescales due to reduced access and increased data transfer rates, leading to high costs for debug units and ports, and incomplete system-level debugging.
Innovation Solution
An integrated circuit chip with a plurality of peripheral circuits connected to respective debug units that generate and stream debug information to separate stores, utilizing a shared hub for resource sharing and signal routing, allowing for a single trigger signal to initiate debug information streaming at a higher rate than output, and employing circular buffers for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple core devices are integrated onto a single chip to form SoC, then product size is reduced and functionality is enhanced, but access for external debugging tools is reduced and data transfer rate requirements increase
Solution Approach 1:
The patent introduces an intermediary debug unit and buffer store mechanism between the core devices and external debugging tools. This intermediary layer collects debug information from multiple cores via internal buses and stores it in buffers, enabling external tools to access debug data without direct connection to the chip's internal bus architecture. This resolves the contradiction by providing a mediator that bridges the gap between integrated chip architecture and external debugging requirements.
2Difficulty of detecting and measuring
If debug units are provided for each core device to enable independent monitoring, then debugging capability is improved, but silicon area cost increases
Solution Approach 1:
The patent implements a universal debug unit that can monitor multiple core devices rather than dedicated debug units for each core. The debug unit collects debug information from various cores through the internal bus infrastructure, making it multi-functional. This universality reduces the total number of debug units required, thereby reducing silicon area consumption while maintaining comprehensive debugging capability across all core devices.
3Reliability
If debug information is streamed at high rate to capture all data, then complete system-level debug is achieved, but data transfer bandwidth requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-storing debug information in buffers at high rate before the actual debugging analysis phase. The buffer store mechanism captures and stores debug data continuously at high rate, allowing the system to later process and analyze this pre-collected data at controlled rates. This preliminary buffering action enables complete system-level debug to be achieved without requiring continuous high bandwidth transfer during the analysis phase, as the data is already prepared in the buffers.
Data Source
AI summary
Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.