RC Tech File Generation via Pattern-Based Capacitance Extraction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing RC technology file generation process is highly CPU-intensive and time-consuming, requiring numerous hours or days to create hundreds or thousands of RC tech files needed for advanced integrated circuit (IC) design projects, especially in supporting IC design projects with varying technology nodes and process corners.
Innovation Solution
A method and system for generating RC technology files that involve identifying common conductive feature patterns, creating pre-characterized capacitance models, and assembling these models to reduce computational intensity and generate capacitance tables, allowing for the reuse of parasitic capacitance values across similar conductor configurations, thereby reducing the time and resources required for RC tech file preparation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional field solver is used to extract capacitance for every conductor primitive, then extraction accuracy is maintained, but computational time and CPU intensity become excessively high
Solution Approach 1:
The patent segments the IC layout into distinct conductor primitives and groups them into conductive feature patterns. By dividing the complex layout into manageable segments that can be processed independently, the system enables selective capacitance extraction only where needed, reducing overall computational time while maintaining accuracy for critical areas.
Solution Approach 2:
The patent performs preliminary identification and grouping of conductive features into patterns before executing the full capacitance extraction. This preliminary classification allows the system to pre-determine which conductors require full field solver analysis and which can use simplified models, thereby reducing total computation time while preserving extraction accuracy for essential conductors.
2Adaptability or versatility
If hundreds or thousands of RC tech files are generated for different technology nodes and process corners, then design coverage is improved, but productivity and resource utilization deteriorate
Solution Approach 1:
The patent creates a universal framework for identifying conductive feature patterns that can be applied across multiple technology nodes and process corners. By establishing generalizable pattern recognition rules and shared capacitance models, the system enables a single analysis to serve multiple design scenarios, reducing the need to regenerate files for each variant while maintaining comprehensive design coverage.
Solution Approach 2:
The patent employs parameter variation techniques where capacitance models are adjusted based on process corner and technology node parameters rather than regenerating from scratch. By modifying existing models through parameter changes rather than complete re-extraction, the system maintains design coverage for different scenarios while dramatically improving generation efficiency and resource utilization.
3Reliability
If redundant capacitance calculations are performed for similar conductor configurations, then completeness is ensured, but computational resource consumption increases
Solution Approach 1:
The patent merges similar conductor configurations into unified conductive feature patterns. By combining conductors with identical or substantially similar geometric and environmental characteristics into single patterns, the system extracts capacitance once per pattern rather than for each individual conductor, ensuring completeness through comprehensive pattern coverage while eliminating redundant calculations and reducing computational resource consumption.
Data Source
AI summary
A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.