Deadlock Detection in Integrated Circuit Power Nodes
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Solution Overview
Problem
Current methods for integrated circuit design verification, particularly in digital/analog mixed-signal circuits, are inefficient and inaccurate in detecting deadlocks between circuit modules, as static verification only detects potential errors and simulations are time-consuming for large designs, often missing deadlocks between modules.
Innovation Solution
A deadlock detection method that retrieves power nodes, determines a starting order, and performs deadlock detection using a resource allocation graph algorithm to identify potential deadlocks in circuit paths, enabling efficient and accurate verification across all circuit modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation is used to verify circuit behavior, then accuracy of detecting circuit operations is improved, but verification time increases significantly for large designs
Solution Approach 1:
The verification process is segmented into two distinct phases: static verification for individual circuit modules (fast, accurate for modules) and deadlock detection for inter-module interactions (fast, accurate for system-level deadlocks). This segmentation allows each phase to optimize for its specific purpose without the time penalty of full-system simulation.
Solution Approach 2:
Static verification is performed as a preliminary action before deadlock detection. By first verifying each circuit module individually using static methods, the system prepares the foundation for subsequent deadlock detection, eliminating the need for time-consuming simulations to verify basic module functionality.
2Productivity
If static verification is used to check potential errors, then verification speed is improved, but detection accuracy of functional errors deteriorates
Solution Approach 1:
The verification capabilities are segmented between static verification (fast, detects potential errors within modules) and deadlock detection (fast, detects functional deadlocks between modules). Each method operates in its optimal domain, maintaining high speed while ensuring comprehensive error detection through the combination of both approaches.
Solution Approach 2:
The deadlock detection mechanism acts as an intermediary that bridges the gap between static verification and full simulation. It takes the circuit design file and module verification results as input, and provides deadlock detection output, thereby extending the capabilities of static verification to detect functional deadlocks without requiring time-consuming simulations.
3Productivity
If each circuit module is verified separately, then verification efficiency for individual modules is improved, but detection of deadlocks between modules deteriorates
Solution Approach 1:
The verification process is segmented into module-level static verification and system-level deadlock detection. Module-level verification maintains high efficiency for individual modules, while the subsequent deadlock detection phase ensures reliability by specifically checking for inter-module deadlocks that would be missed in isolated module verification.
Solution Approach 2:
The deadlock detection mechanism provides feedback about inter-module interactions that complements the module-level verification results. By analyzing the circuit design file and module verification outcomes, the system generates feedback information about potential deadlocks between modules, thereby enhancing overall verification reliability without sacrificing module-level efficiency.
Data Source
AI summary
A deadlock detection method includes: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path. A non-transitory machine readable medium stores a program code, wherein when executed by a processor, the program code enables the processor to perform the following steps: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path.