Parasitic Model Evaluation with Varying Accuracy Modes
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Solution Overview
Problem
Current analog and mixed-signal design methodologies for RF and high-performance analog circuits are inadequate in accounting for parasitic effects early in the design cycle, leading to repeated iterations between circuit sizing and layout, and are cumbersome due to manual estimation and limited support for parasitic information from layouts.
Innovation Solution
The solution involves automated techniques for evaluating and backannotating parasitic models between schematic and layout environments, allowing users to select simulation modes with varying accuracy and mix-and-match schematic and layout parasitic information, enabling parasitic analysis during circuit design and layout creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual parasitic estimation on schematic is used, then the design process is simple, but the accuracy of parasitic analysis is insufficient for RF and high-performance analog designs
Solution Approach 1:
The system performs preliminary parasitic extraction from layout data before the design is finalized, allowing parasitic effects to be accounted for early in the design cycle. This enables designers to evaluate parasitic impacts on circuit performance before committing to the final layout, thus improving accuracy without requiring complete manual estimation processes.
Solution Approach 2:
The patent introduces an intermediary system that connects layout data with circuit simulation. This intermediary automatically extracts parasitic information from layout geometries and integrates it with schematic-level circuit simulations, bridging the gap between simple schematic analysis and complex extracted analysis without requiring manual intervention.
2Measurement precision
If parasitic extraction from completed layout is performed, then accurate parasitic information is obtained, but the process is time-consuming and requires complete layout
Solution Approach 1:
The system performs parasitic extraction preliminarily from partial or incomplete layout data before the design is finalized. This allows accurate parasitic information to be obtained early in the design process without waiting for the complete layout, enabling iterative design optimization without time-consuming re-extraction cycles.
Solution Approach 2:
The patent enables parasitic extraction from partial layout data rather than requiring complete layout. This partial action approach allows designers to extract parasitic information from available layout portions and use it for circuit optimization, avoiding the need to wait for the entire layout to be completed.
3Reliability
If multiple iterations between circuit sizing and layout are performed, then design specifications are met, but the design cycle becomes lengthy and cumbersome
Solution Approach 1:
The system performs preliminary parasitic analysis early in the design cycle using available layout data, allowing circuit sizing to account for parasitic effects before final layout completion. This reduces the need for multiple iteration cycles between sizing and layout by providing accurate parasitic information upfront.
Solution Approach 2:
The patent implements a feedback mechanism where parasitic extraction results are automatically fed back to circuit simulation and sizing tools. This continuous feedback loop allows real-time adjustment of circuit parameters based on parasitic measurements, reducing the number of iterative cycles needed to meet design specifications.
4Productivity
If automated parasitic extraction and backannotation is implemented, then the process efficiency is improved, but the system complexity increases
Solution Approach 1:
The patent creates a universal system that performs multiple functions: parasitic extraction from layout, backannotation to schematic, integration with circuit simulation, and support for iterative design. This multi-functional system consolidates what would otherwise be separate manual processes into a single automated platform, improving efficiency despite increased system complexity.
Solution Approach 2:
The system performs self-service by automatically extracting parasitic information from layout data and backannotating it to the schematic without requiring manual intervention. The automated workflow manages the entire parasitic analysis process, from extraction to integration with circuit simulation, reducing the need for manual parasitic estimation and analysis steps.
Data Source
AI summary
A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.