Multi-Level IC Debugging Synchronization
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Solution Overview
Problem
Current IC design debugging processes are inefficient due to the need for manual translation and debugging between register transfer level (RTL) and gate level designs, leading to significant time expenditure and bottlenecks in chip design.
Innovation Solution
A method and system for synchronously debugging designs at multiple levels by providing signal correlation information and using multiple processes or threads to load and manage design descriptions in separate windows, allowing for automatic selection and synchronization of signals across design levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If designers manually debug designs at gate level after synthesis, then design issues can be discovered and resolved, but debugging time increases significantly
Solution Approach 1:
The patent merges RTL-level and gate-level debugging interfaces into a single unified debugging session. The system presents both design levels simultaneously with synchronized signal views, allowing designers to switch between levels without manual translation or separate debugging processes, thus resolving design issues faster while maintaining reliability
Solution Approach 2:
The patent introduces a synthesis tool intermediary that automatically translates and correlates signals between RTL and gate levels. This intermediary establishes signal correspondence relationships, enabling automatic signal selection across design levels and eliminating manual debugging translation work, thereby reducing debugging time while maintaining accurate design issue detection
2Loss of information
If designers trace signals between RTL and gate levels manually, then signal correspondence can be established, but the process becomes a technological bottleneck
Solution Approach 1:
The patent performs preliminary signal correspondence establishment during the synthesis process itself. The synthesis tool automatically creates and stores signal correlation information between RTL and gate levels before debugging begins. This preliminary action eliminates the need for manual signal tracing during debugging, maintaining complete signal correspondence information while removing the productivity bottleneck
Solution Approach 2:
The patent creates a virtual copy of the RTL design at the gate level with maintained signal correspondence. The debugging system presents synchronized views of both design levels, allowing designers to trace signals at either level with automatic translation. This copying approach preserves signal correspondence information while enabling parallel debugging operations that eliminate the sequential bottleneck
3Ease of operation
If separate debugging processes are used for RTL and gate levels, then each design level can be debugged independently, but synchronization and coordination become complex
Solution Approach 1:
The patent merges separate RTL and gate-level debugging processes into a single integrated debugging session. The system maintains independent debugging capabilities for each design level while providing automatic synchronization of signal views and coordinated control. This merging approach preserves the ease of independent debugging operations while eliminating the complexity of manual synchronization and coordination between separate processes
Data Source
AI summary
Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected.