Signal Tracing Across Boards and Chips for Failure Analysis
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Solution Overview
Problem
Failure analysis of printed circuit boards and semiconductor chips is challenging due to their complexity, with hundreds of millions of transistors on chips and thousands of wires on boards, making it difficult to identify defective signals and defects.
Innovation Solution
A computer-implemented method for signal tracing across boards and chips, involving importing layouts, tracing signal paths through active and passive circuitry, and displaying the paths to identify defects, which includes simulating and aligning test equipment to inspect potential failure points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If signal tracing is performed across complex boards and chips with hundreds of millions of transistors and thousands of wires, then defect identification capability is improved, but analysis time and computational resources increase significantly
Solution Approach 1:
The patent segments the complex signal tracing problem by dividing the board and chip into hierarchical levels (package levels). It traces signals across discrete boundaries between these levels, breaking down the overwhelming complexity into manageable segments that can be analyzed separately and then integrated, thereby reducing analysis time while maintaining defect identification capability.
Solution Approach 2:
The patent performs preliminary actions by pre-importing and storing layout information for multiple package levels before actual signal tracing begins. This preparatory step organizes the complex data structure in advance, creating a ready-to-query framework that accelerates subsequent defect analysis without requiring real-time computation across the entire complex system.
2Measurement precision
If comprehensive signal tracing is performed through all circuitry including active devices and passive components, then defect detection accuracy is improved, but device complexity and data processing requirements increase
Solution Approach 1:
The patent segments the tracing process by treating active circuitry (transistors, logic gates) and passive components (resistors, capacitors, wires) as distinct elements with different tracing rules. This segmentation allows the system to apply appropriate analysis methods to each type, improving defect detection accuracy while managing data processing complexity through specialized handling of each component category.
Solution Approach 2:
The patent creates a universal tracing framework that can handle multiple types of components (active and passive) through a single integrated system. This multi-functional approach allows comprehensive defect detection across all circuitry types while avoiding the need for separate complex processing systems for each component type, thereby managing overall data processing complexity.
3Measurement precision
If multiple package levels are integrated into a single analysis framework, then cross-boundary defect identification is improved, but system complexity increases
Solution Approach 1:
The patent segments the multi-level package system into distinct package levels (first package level, second package level, etc.) with clearly defined boundaries. This segmentation allows the system to import and manage layout information for each level separately while maintaining their spatial relationships, thereby enabling cross-boundary defect identification without overwhelming system complexity.
Solution Approach 2:
The patent adds a hierarchical dimension to the analysis framework by organizing package levels in a multi-layered structure. This dimensional approach allows simultaneous tracking of signals across multiple physical levels while maintaining logical organization, improving cross-boundary defect identification capability while managing system complexity through structured hierarchical representation.
Data Source
AI summary
Signal tracing across boards and chips can be used to greatly enhance failure analysis of the boards and chips. Concepts are disclosed for tracing one or more signal lines across a board, across a chip boundary, and across a chip. Signals may be traced through active circuitry on a chip along with paths through various logic cones. The result can be graphically and interactively presented.