Multi-Core Processor Error Management via Core Swapping
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Solution Overview
Problem
High-performance computing systems with multiple processor cores face critical failures when one core fails, leading to system crashes and increased workload on remaining cores, with existing software solutions failing to effectively manage core failures and consider layout impacts on system health and throughput.
Innovation Solution
A method for managing hardware errors in multi-core environments by allocating processor cores into main and spare sets, using a main hardware description table and a spare hardware description table, where spare cores are abstracted from the operating system and reserved for computational tasks, allowing for processor core swapping and error handling without disrupting the operating system, using a message passing interface and embedded firmware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor cores are allocated to enable state for active computing, then system productivity is improved, but system reliability deteriorates because failure of any core causes entire system failure
Solution Approach 1:
The patent segments processor cores into two distinct groups: enabled cores (first subset) and spare cores (second subset). This segmentation allows the system to maintain active computing with enabled cores while having dedicated backup cores available to replace failed ones, thus resolving the contradiction between productivity and reliability.
Solution Approach 2:
The patent performs preliminary action by pre-allocating spare processor cores before any failure occurs. These spare cores are reserved and configured in advance, so when a failure happens, replacement can occur immediately without system disruption, maintaining both productivity and reliability.
2Ease of operation
If software solutions are used to manage processor core errors, then ease of operation is improved, but device complexity increases and workload overhead increases
Solution Approach 1:
The patent implements self-service by enabling processor cores to automatically detect and manage their own failures through built-in error detection logic. The system autonomously identifies failed cores, selects appropriate spare cores, and performs replacement without requiring complex external software management, thus improving ease of operation while reducing device complexity.
3Productivity
If processor cores are densely packed to increase computing power, then productivity is improved, but reliability deteriorates due to increased stress on adjoining cores and tiles
Solution Approach 1:
The patent applies local quality by allowing different regions of the processor die to have different functional assignments. Specifically, certain cores are designated as spare cores with potentially different operational characteristics, enabling them to serve as buffers that protect the main computing cores from stress propagation, thus maintaining reliability while preserving computing power.
Data Source
AI summary
A method and device for managing hardware errors in a multi-core environment includes allocating processor cores to a main set and a spare set of processor cores. The main set of processor cores are used by an operating system, and the spare set of processor cores are dedicated to software applications. Should a processor core error occur, a processor core swap may be performed to swap a spare processor core for a failing main processor core without interrupting the execution of the operating system.