Trace Bandwidth Estimation for SoC CoreSight Architecture
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Solution Overview
Problem
Current methods for estimating trace bandwidth requirements in System on a Chip (SoC) design are inadequate, particularly when firmware and hardware models are not available, leading to delays and inaccuracies in architectural decisions, which can result in missed market windows and ineffective debug trace systems.
Innovation Solution
A software program that allows users to input design parameters to determine the feasibility of a proposed trace architecture by analyzing FIFO levels, overflow incidents, and data suppression events, providing quick estimates of trace bandwidth requirements before firmware and hardware models are developed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ESL methods or simulations are used to evaluate SoC design, then measurement precision is improved, but device complexity and time consumption increase significantly
Solution Approach 1:
The patent creates a simplified, lightweight estimation tool that provides adequate trace bandwidth estimates without requiring complex ESL simulations. This disposable estimation approach suffices for early architectural decisions, reserving complex simulations only for final verification stages when accuracy is critical.
Solution Approach 2:
The estimation process is segmented into distinct phases: early architectural estimation using simple formulas, and final verification using complex simulations. This segmentation allows each method to be applied at the appropriate stage, avoiding unnecessary complexity during early design when firmware and detailed hardware models are unavailable.
2Measurement precision
If firmware and hardware models are available for simulation, then measurement precision is improved, but loss of time increases due to waiting for firmware completion
Solution Approach 1:
The patent enables preliminary trace bandwidth estimation to be performed using only basic architectural parameters (trace port width, clock speeds, bus activity estimates) before firmware is completed. This preliminary action allows architectural decisions to be made early, eliminating the need to wait for firmware development while maintaining sufficient accuracy for initial design choices.
3Loss of time
If estimation is made early without firmware, then loss of time is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent applies partial action by using only the essential parameters needed for rough estimation (trace port width, clock speeds, basic bus activity) rather than waiting for complete firmware and detailed hardware models. This partial information approach provides sufficient accuracy for early architectural trade-off decisions without requiring exhaustive data.
4Device complexity
If hand calculations are used for estimation, then device complexity is reduced, but loss of time increases due to tedious and error-prone processes
Solution Approach 1:
The patent replaces manual hand calculations with an automated software tool that performs trace bandwidth estimation using simple formulas. This substitution eliminates the tedious, error-prone nature of manual calculations while maintaining the simplicity and transparency of the estimation method, providing results quickly and accurately.
Data Source
AI summary
A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.