Semiconductor Mask Design for White Bump Prevention
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Solution Overview
Problem
Current methods lack a tool to predict and prevent 'white bumps' and resulting wiring layer delamination in semiconductor chips during packaging due to thermal coefficient mismatch and stress transfer from lead-free solder interconnects, leading to potential failure points that are not identified until after the assembly process.
Innovation Solution
A failure analysis tool and method that determine the risk area for wiring layer failure by calculating distances and radii for solder bump formation, identifying critical areas, and using this data to design a mask for reinforcing vulnerable structures like vias in the copper levels of the chip, thereby reducing stress and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lead-free solder interconnects (tin/copper, tin/silver, SAC alloys) are used to replace leaded solder, then lead-free requirements are met, but low ductility causes stress transfer through C4 joint during assembly process leading to wiring layer delamination and white bumps
Solution Approach 1:
The patent applies preliminary action by identifying and reinforcing critical wiring areas before the soldering process. The system calculates stress distribution patterns and pre-reinforces vulnerable wiring layers with additional material or structural support, so that when lead-free solder is applied, the pre-prepared wiring can withstand the stress without delamination or white bump formation.
2Manufacturing precision
If high temperature soldering process (250°C to 260°C) is used to form C4 bumps, then solder interconnects are successfully formed, but thermal expansion mismatch between organic laminate (TCE 18-20) and chip (TCE 2) causes tensile stresses during cooling cycle
Solution Approach 1:
The patent applies parameter changes by modifying the thermal properties of the wiring structure. The system identifies areas where wiring layers need enhanced thermal stress resistance and adjusts material parameters (such as adding stress-compensating layers or modifying material composition) in those specific regions, allowing the wiring to better accommodate thermal expansion mismatch during the soldering and cooling process.
3Productivity
If no predictive tool is used for white bump location, then packaging process proceeds without additional steps, but failure points are not identified until after assembly process
Solution Approach 1:
The patent applies feedback by creating a closed-loop system that uses finite element analysis to calculate stress distribution patterns during soldering. The system provides feedback information about predicted white bump locations and critical wiring areas, which then guides the reinforcement process. This feedback mechanism enables early identification of failure points while maintaining packaging process efficiency through automated analysis.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively identifies and reinforces critical areas before packaging, reducing the likelihood of delamination and maintaining wiring integrity by using a mask to apply hard dielectric or soft passivation between C4 bumps and BEOL metalization, thus preventing 'white bumps' and ensuring robust chip connections.
Implementation Method 1
As the package (laminate, solder and chip) begins to cool, the solder begins to solidify (e.g., at about 180° C.)
Implementation Method 2
the laminate begins to shrink as the chip remains substantially the same size
Implementation Method 3
the organic laminate has a TCE of about 18 to 20; whereas, the TCE of the chip is about 2. During the soldering process, e.g., reflow oven, the temperatures can range from about 250° C. to 260° C. This high temperature expands the organic laminate more than the chip
Data Source
AI summary
A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.