Circuit Simulation Replay Module for Event Timing
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Solution Overview
Problem
Modern integrated circuit testing using hardware description languages (HDLs) faces challenges due to non-deterministic event timing, leading to false negatives in simulation results, as the order of events within a timestamp is not consistently captured, causing incorrect application of input signals during testing.
Innovation Solution
A method and system for simulating circuit designs by generating an initial representation, capturing event data with timestamps, reordering events, and creating a replay module to ensure correct timing and ordering of input signals, thereby preventing false negatives during simulation testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a testbench is used to verify core behavior with pre-determined input sequences, then verification capability is improved, but non-deterministic event timing causes false negatives in testing
Solution Approach 1:
The patent applies preliminary action by pre-determining the correct order of events at each timestamp before execution. The system analyzes all events scheduled at a given timestamp in advance, determines their correct chronological order based on simulation semantics, and stores this ordered sequence. During replay, this pre-determined order ensures events are applied correctly without non-deterministic variations, eliminating false negatives while maintaining verification capability.
2Loss of information
If events are captured with timestamps in simulation, then timing information is preserved, but reordering events at the same timestamp is necessary to prevent false negatives
Solution Approach 1:
The patent applies segmentation by dividing events into groups based on their timestamps. All events occurring at the same timestamp are segmented into a separate group, which is then processed independently to determine the correct internal ordering. This segmentation allows the system to preserve timestamp information while applying complex reordering logic only where needed (at multi-event timestamps), rather than reordering all events universally.
3Productivity
If a replay module is generated to reproduce test stimuli, then test reuse is improved, but incorrect event ordering in the replay module causes false negatives
Solution Approach 1:
The patent applies copying by creating an accurate replica of the original simulation's event sequence. The system captures the complete ordered sequence of events from the initial simulation, including the correct chronological order at each timestamp, and stores this as a replay module. This copy can then be reused to reproduce test stimuli exactly as originally executed, ensuring test reuse efficiency without introducing false negatives from event ordering variations.
Data Source
AI summary
A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.