Segmented voltage electrodes resolve axial resolution limits in core plug measurements by detecting small resistivity anomalies.
Constant-current impulse ratio calibration reduces testing time from 26 hours to 6 hours while maintaining accuracy through neural network modeling.
A measurement device applies pulse currents to laminated bodies and acquires in-plane magnetic field distribution information for internal analysis.
Coordinate graph visualizes semiconductor wafer probe contact parameters for simplified setting.
A battery monitoring system retrieves precomputed estimation parameters from a database to process cell data in real time.
A corrector circuit generates a correction current to offset temperature-dependent on-resistance in the main transistor.
A battery management unit dynamically adjusts measurement data resolution and frequency to optimize bus system bandwidth utilization.
A Gaussian Process regression model combines stationary and non-stationary kernels to estimate health metrics from sensor data.
A replay module reorders input signals to ensure correct timing during circuit simulation.
Two-step channel calibration corrects sampling capacitor errors, reducing system size and cost while improving state of charge accuracy.
A cabinet charging station uses dynamic locking to secure mobile devices while enabling rapid user access.
Dedicated data channels enable accurate chip-by-chip testing of stacked semiconductor apparatuses, resolving mixed data levels from shared channel outputs.
An electrically floating substrate carrier structure decouples the support from ground to minimize electrostatic discharge during handling.
Mixed membership model computes topic and feature distributions from scan diagnostic reports to identify failure mechanisms in integrated circuits.
Extracting dQ/dV curves under complex conditions ensures accurate battery life degradation analysis with minimal memory usage.
A testing apparatus uses a separate PCB and socket to install flash memory chips for direct signal connection.
A state of charge determination method uses filtered open-circuit voltage to correct current integration errors.
Differential equation model tracks electrolyte density and potential to forecast self-discharge, reducing unnecessary maintenance charging.
A memory interface circuit shifts test addresses to actual array locations using configurable offset values.
Automated energy management adjusts charge limits by state of health to improve measurement precision while maintaining battery availability.
An inspector calculates error values between recorded set and reset pressures against factory defaults to identify precision decline in fluid circuit actuators.
A message interceptor extracts standardized substation data from IED traffic for automated consistency verification.
A battery state detection method uses preset discharge conditions to measure partial discharge data for direct calculation of health and charge metrics.
Optocoupler isolation in this measuring device eliminates capacitive interference, enabling accurate detection of test section states.
Applying opposite polarity electrical biases to a thermopile isolates sensitivity by canceling resistance voltages without external heaters.
Method predicts membrane electrode assembly life using derived accelerated degradation operating conditions.
A three-dimensional electrochemical model simulates lithium ion concentration across battery regions to enable precise state monitoring.
Multi-thread architecture updates observable and unobservable estimators independently to reduce time consumption while maintaining accuracy.
Processor-based system detects real-time voltage and current to estimate battery health.
Estimate mapping between transistor parameters and logic block measurements to extract die-level electrical data without additional testing.
A fuseROM controller links memory wrappers via a bypass chain to load repair data selectively.
A semiconductor testing system manages rule creation and execution through dedicated modules.
A hybrid deep neural network architecture estimates battery state of health using supervised and unsupervised learning methods.
Mapping parameters correlate voltage variation with battery state of health, enabling accurate capacity calculation without full discharge cycles.
A battery state estimating unit corrects open-circuit voltage characteristics by adjusting model parameters based on detected estimation errors.
A flat plate probe uses an elastic body part to contact pads on a semiconductor wafer.
Electronic control unit calculates surface stress from battery use history to correct estimated open circuit voltage values.
An energy storage device powers a signal light unit to change illumination status when heat trace cables fail, facilitating inspection.
Segmented wrappers share registers with adjacent logic circuits to extend test signals, resolving untested chip regions as integration increases.
Exposing parity difference information allows a test system to classify correctable and uncorrectable errors in one run, eliminating multiple test modes.
A controller filters low battery current values to calculate a reliable charging resistance equivalent for state of health assessment.
Classify battery cells using charge profile algorithms to prevent overcharging and thermal runaway in packs.
A method maps hardware netlists to target graphs for automatic functional primitive detection.
A sensor circuit measures battery internal resistance to dynamically adjust voltage thresholds during charging cycles.
Sliding time windows segment battery cell voltage data to reduce computational load while minimizing misdiagnosis rates from extreme values.
A detection assembly moves along a linear direction to measure electrical parameters at battery nickel tab weld positions.
A photovoltaic control system adjusts load parameters using conductance logarithm measurements.
A configurable switch dynamically routes transactions between proxies and verification components in an emulator system.
Modular spade clips and removable wire harnesses simplify series coupling of battery cells while reducing assembly complexity for voltage sensing integration.
A complementary MOS circuit detects high impedance states by forcing nodes to low potential, eliminating bias current while maintaining reliable logic levels.