Memory Device Test Time Reduction via Parity Information
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Solution Overview
Problem
Current memory device testing methods are inefficient due to the need for multiple test modes with and without error correction, leading to increased time and cost, as they struggle to accurately classify devices based on error rates without significant time and cost additions.
Innovation Solution
Exposing parity/difference information generated from data and parity bits to a test system, allowing for the identification of both correctable and uncorrectable errors in a single test with error correction enabled, thereby reducing the number of test runs and improving testing speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple test modes are used to test memory devices with and without error correction, then testing accuracy is improved, but test time increases
Solution Approach 1:
The patent combines multiple test modes into a single integrated test mode where error correction is enabled. The test system simultaneously performs tests that would traditionally require separate test runs, allowing both correctable and uncorrectable errors to be detected in one operation. This merging of test functions reduces test time while maintaining comprehensive testing accuracy through the use of parity/difference information.
Solution Approach 2:
The patent segments the testing process by separating the detection of correctable errors from uncorrectable errors through the use of parity/difference information. By exposing this intermediate information to the test system, the testing process can efficiently identify different error types without requiring multiple complete test cycles, thus reducing overall test time while maintaining accuracy.
2Productivity
If error correction is disabled during testing, then test speed is improved, but testing completeness deteriorates
Solution Approach 1:
The patent introduces parity/difference information as an intermediary element that enables comprehensive testing while maintaining speed. This intermediate data structure allows the test system to quickly identify both correctable and uncorrectable errors without requiring slow, traditional multiple-mode testing. The parity/difference information acts as a mediator that preserves test speed while enhancing testing completeness.
3Ease of operation
If test systems classify devices based on single error existence, then classification simplicity is improved, but classification accuracy deteriorates
Solution Approach 1:
The patent changes the classification parameter from a simple binary (error present/absent) to a more nuanced approach using parity/difference information. This allows the test system to differentiate between correctable and uncorrectable errors, providing more accurate classification. The classification process remains relatively simple by using the exposed parity information as the basis for determination, thus maintaining ease of operation while improving accuracy.
Data Source
AI summary
In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.