Die-Level Electrical Parameter Extraction via Logic Block Mapping
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Solution Overview
Problem
Wafer-level testing in IC fabrication is insufficient for obtaining die-level electrical parameters of each die, as the number of test sites is much smaller than the number of dies, making it difficult to extract die-level electrical parameters such as leakage currents of different transistor types from measurement results of logic blocks.
Innovation Solution
A method and apparatus that estimate a mapping relationship between electrical parameters of transistor types and measurement results of logic blocks, using a processor and non-transitory machine-readable medium to obtain die-level measurement results and generate die-level electrical parameters through matrix inversion and AI modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafer-level testing is used, then testing cost is reduced and defective wafers can be identified, but die-level electrical parameters cannot be obtained for each individual die
Solution Approach 1:
The patent introduces logic block measurement results as an intermediary to bridge the gap between wafer-level testing and die-level parameter extraction. By measuring logic blocks at the die level and using the estimated mapping relationship, the system can derive transistor-level electrical parameters without requiring direct measurement of each transistor, thus resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent replaces direct physical measurement of transistor electrical parameters with a computational approach using logic block measurements and estimated mapping relationships. This substitution allows extraction of die-level electrical parameters through data processing rather than requiring additional physical testing infrastructure, maintaining measurement precision while reducing device complexity
2Measurement precision
If the number of WAT sites is increased to cover more dies, then die-level parameter extraction becomes possible, but testing cost and time increase
Solution Approach 1:
The patent extracts die-level electrical parameters from logic block measurement results using the estimated mapping relationship. This extraction approach allows obtaining transistor-level parameters without performing additional testing on each transistor, thereby maintaining high productivity while achieving accurate die-level parameter extraction
Solution Approach 2:
The patent performs preliminary estimation of the mapping relationship between logic block measurements and transistor electrical parameters. This preliminary action enables subsequent efficient extraction of die-level parameters without requiring re-testing or additional measurement sites, thus preserving testing efficiency while improving measurement precision
Data Source
AI summary
A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.