Memory Interface Circuit Address Shifting for Semiconductor BIST
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with memory BIST functions face increased test time, leading to potential delays and higher costs due to the need for extended testing periods.
Innovation Solution
Incorporating a memory interface circuit that shifts test addresses for each memory array based on set offset values, allowing for simultaneous testing of fewer cells and optimizing power consumption during the test process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If test timings of memory groups are shifted from each other, then power consumption during test is reduced, but test time is increased
Solution Approach 1:
The patent divides the memory array into multiple memory groups and uses multiple pattern generators to test different groups simultaneously. Each pattern generator tests a specific memory group in parallel, allowing the entire memory array to be tested faster while controlling power consumption by managing which groups are active at each timing.
Solution Approach 2:
The patent introduces a new dimension of control by using multiple pattern generators operating in parallel with different test timings. Instead of sequentially testing memory groups in a single dimension of time, the system distributes testing across multiple pattern generators that can operate simultaneously on different memory groups, effectively adding a parallel processing dimension to the test architecture.
2Loss of time
If multiple memory groups are tested simultaneously, then test time is reduced, but power consumption during test is increased
Solution Approach 1:
The patent dynamically controls the test timing of each memory group through multiple pattern generators. The control circuit adjusts when each pattern generator activates its corresponding memory group, allowing flexible optimization of both test time and power consumption. This dynamic timing control enables the system to balance parallel testing with power management.
Solution Approach 2:
The patent changes the timing parameter of test operations for different memory groups. By adjusting the test timing of each pattern generator independently, the system can control the number of simultaneously active memory groups, thereby managing power consumption while maintaining efficient test throughput.
3Device complexity
If a single pattern generator is used for all memory groups, then device complexity is reduced, but test time is increased
Solution Approach 1:
The patent makes each pattern generator universal by designing them to perform the same test functions on different memory groups. Each pattern generator can independently test its assigned memory group using identical test sequences and control logic, allowing the system to scale by adding more identical units rather than designing complex custom test circuits for each group.
Solution Approach 2:
The patent uses multiple copies of the same pattern generator circuit for testing different memory groups. Instead of creating a single complex pattern generator that handles all groups sequentially or requiring custom circuits for each group, the system replicates the pattern generator unit multiple times, with each copy dedicated to a specific memory group, simplifying the overall design while enabling parallel testing.
Data Source
AI summary
To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.