Flash Memory Testing Apparatus With Segmented PCB And Socket
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Solution Overview
Problem
Traditional methods for testing and replacing embedded memory chips on printed circuit boards are time-consuming, damage-prone, and lack dedicated testing points for NAND flash memory signals, especially due to the close packaging and lack of space for FBGA sockets, which complicates signal separation between eMMC and DDR memory.
Innovation Solution
A testing apparatus comprising an interface PCB with dedicated NAND flash and eMMC pins, a separate PCB for signal separation, and a socket device that allows direct installation and replacement of eMMC/eMCP/CiMCP chips, enabling precise alignment and connection without damaging the PCB, and separating eMMC signals from DDR memory signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FBGA socket is installed on the soldering point of the eMMC/eMCP/CiMCP chip, then the chip can be placed into the socket for testing, but the device size becomes very large and no testing points for eMMC signals are available
Solution Approach 1:
The patent divides the testing system into two separate parts: a FBGA socket for mechanical chip support and a separate PCB with test points for electrical signal testing. This segmentation allows each component to be optimized independently - the socket provides reliable chip mounting while the separate PCB provides accessible test points without adding overall system complexity.
Solution Approach 2:
The patent introduces a separate PCB as an intermediary between the FBGA socket and the test equipment. This intermediary PCB contains the necessary test points and circuitry, allowing signal testing without requiring the main socket device to be oversized or complex.
2Reliability
If the insulation layer of the PCB is exposed and additional wires are soldered onto the PCB to test eMMC signals, then signal testing becomes possible, but the PCB is damaged resulting in testing failure
Solution Approach 1:
The patent pre-configures the separate PCB with all necessary test points, traces, and connections before it is needed for testing. This preliminary preparation eliminates the need for damaging modifications during the testing process, as the PCB is already ready to receive and route signals properly.
Solution Approach 2:
The patent creates a separate PCB that copies the necessary signal paths and test point configurations from the original PCB design. This allows testing to be performed on the copy without damaging the original PCB, preserving the integrity of the main board while enabling comprehensive signal testing.
3Ease of operation
If eMMC/eMCP/CiMCP chip is unloaded from the PCB and a FBGA socket is installed, then the chip can be replaced easily, but the process takes a very long time
Solution Approach 1:
The patent merges the FBGA socket mounting function with the signal testing function by integrating them into a unified testing apparatus. The chip is mounted once on the socket, which is then connected to the separate PCB, allowing both mechanical support and electrical testing to occur simultaneously, eliminating the need for repeated unloading and reloading operations.
Solution Approach 2:
The patent prepares the FBGA socket with the chip mounted beforehand, and pre-configures the separate PCB with all necessary connections and test points. This preliminary preparation allows the actual replacement and testing operation to be completed quickly without time-consuming setup steps during the replacement process.
4Area of stationary object
If eMMC chip and DDR memory are packaged together in eMCP/CiMCP chip, then space is saved on PCB, but signals from eMMC chip and DDR memory cannot be separated
Solution Approach 1:
The patent segments the signal paths from the packaged eMCP/CiMCP chip by creating separate connection interfaces on the separate PCB. Even though the chip itself is integrated, the testing system separates the signal routes for eMMC and DDR memory, allowing independent testing of each component without requiring physical separation of the chip components.
Solution Approach 2:
The separate PCB acts as an intermediary that receives signals from the packaged chip and routes them to appropriate test points. This intermediary layer provides signal separation and conditioning, allowing the integrated chip to be tested with separated signal paths despite its compact packaged form.
Data Source
AI summary
A test apparatus for testing a first flash memory chip is provided. The testing apparatus includes: an interface printed circuit board (PCB), a separate PCB, and a socket device. The separate PCB is disposed over the interface PCB, and a second flash memory chip is placed between the interface PCB and the separate PCB. The second flash memory chip includes a first embedded flash memory chip and a dynamic random access memory (DRAM), and the second flash memory chip is connected to the interface PCB through corresponding first pins of the DRAM. The socket device is disposed over the separate PCB and is configured to install the first flash memory chip. The first flash memory chip is connected to the interface PCB through corresponding second pins.