FuseROM Controller Memory Repair Bypass Chain Optimization
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Solution Overview
Problem
The increasing number of memories in SoCs leads to a fuseROM area bottleneck and high autoload time for memory repair, as existing BIST and Efuse solutions require significant space and time, compromising memory reparability and test quality.
Innovation Solution
The integration of memory wrappers with fuse registers and bypass registers, linked by memory data and bypass chains, allows for efficient self-repair and reduced fuseROM area usage by storing and loading repair data only for defective memory blocks, thereby minimizing the size of the fuseROM and autoload time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuseROM is used to store repair data for all memory blocks, then memory reparability is ensured, but fuseROM area becomes excessively large
Solution Approach 1:
The patent segments the memory blocks into two categories: defective memory blocks and non-defective memory blocks. Only defective memory blocks have their repair data stored in fuseROM, while non-defective blocks are identified through bypass data without requiring repair information. This segmentation reduces fuseROM area while maintaining complete memory reparability for defective blocks.
Solution Approach 2:
The patent applies local quality by storing detailed repair data only where needed (in defective memory blocks) while using simplified bypass data for non-defective blocks. The fuseROM controller selectively loads and stores repair information based on the specific condition of each memory block, optimizing space utilization while ensuring appropriate repair capabilities are maintained locally where defects exist.
2Reliability
If repair data is loaded for all memory blocks, then complete memory repair capability is achieved, but autoload time increases significantly
Solution Approach 1:
The patent extracts and separates the loading of bypass data from the loading of repair data. Bypass data, which identifies defective blocks, is loaded first and used to selectively determine which memory blocks require repair. Only then is repair data loaded for the specific defective blocks identified. This extraction eliminates the need to load repair data for all memory blocks, significantly reducing autoload time while maintaining complete repair capability for defective blocks.
Solution Approach 2:
The patent performs preliminary action by first loading and processing bypass data to identify which memory blocks are defective before loading the actual repair data. This preliminary identification step allows the system to prepare selectively, loading only the necessary repair information for defective blocks rather than all blocks, thereby reducing overall autoload time while ensuring repair capability is ready when needed.
3Area of stationary object
If fuseROM size is reduced to save area, then area bottleneck is relieved, but memory test quality may be compromised
Solution Approach 1:
The patent introduces dynamics by making the fuseROM content adaptive rather than static. The fuseROM controller dynamically determines what data to store based on actual memory block conditions. Bypass data is loaded first to identify defective blocks, and then repair data is selectively stored only for those defective blocks. This dynamic approach ensures fuseROM size is minimized while maintaining complete test quality, as the system adapts its storage requirements to the actual defect distribution in the memory array.
Solution Approach 2:
The patent implements feedback through the bypass data mechanism. The bypass data provides information about the status of each memory block, which feeds back to the fuseROM controller to determine what repair data needs to be stored. This feedback loop ensures that fuseROM contains exactly the right amount of information needed for testing and repairing actual defective blocks, maintaining full test quality while minimizing storage requirements based on real memory conditions rather than worst-case assumptions.
Data Source
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AI summary
A memory repair system in an integrated circuit (IC) (100) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers (102). Each memory wrapper (104, 106, 108, 110, 112, 114) includes a memory block (122A-F) with a fuse register (124A-F) and a bypass register (126A-F). The bypass registers have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller (140) is coupled to the plurality of memory wrappers. A memory bypass chain (134) links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain (132) links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.