Insulated Circuit Substrate Layout to Reduce Warping and Cracking

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Solution Overview

Problem

The semiconductor device experiences warping and cracking due to thermal expansion coefficient differences between ceramic and metal components, leading to reduced thermal conductivity and insulating properties, affecting long-term reliability.

Innovation Solution

The semiconductor device incorporates a resin layer with a circuit pattern and base plate, where semiconductor chips are spaced inwardly from the circuit pattern's edge, and a case surrounds the circuit pattern and semiconductor chip, with a sealing material covering the substrate, minimizing thermal expansion coefficient differences and preventing heat interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a ceramic plate is used as the base plate in the insulated circuit substrate, then high thermal conductivity and insulating property are achieved, but warping occurs due to thermal expansion coefficient differences between the ceramic plate and the circuit pattern/metal plate

Engineering Contradiction:
Improvelong-term reliabilityVSAvoidwarping of insulated circuit substrate
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent changes the material parameter of the base plate from ceramic to resin, which has a thermal expansion coefficient closer to that of the circuit pattern and metal plate. This parameter change reduces the thermal expansion mismatch, thereby minimizing warping during heat cycling while maintaining the structural integrity and reliability of the insulated circuit substrate.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure where the resin base plate is combined with circuit patterns and metal plates to create an insulated circuit substrate that balances thermal expansion properties across different materials. This composite approach allows the assembly to expand and contract more uniformly during temperature changes, reducing warping and improving long-term reliability.

Inventive Principle:
Principle #40Composite materials

2Area of stationary object

If the semiconductor chip is bonded close to the edge of the circuit pattern, then space utilization is maximized, but heat interference and thermal stress concentration occur at the edges

Engineering Contradiction:
Improvespace utilizationVSAvoidheat interference and thermal stress
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a spaced arrangement where the semiconductor chip is positioned inward from the edge of the circuit pattern by a predetermined distance. This local spacing strategy concentrates heat management resources (such as heat dissipation paths and stress distribution zones) in critical areas, reducing heat interference and thermal stress concentration at the edges while maintaining efficient space utilization.

Inventive Principle:
Principle #3Local quality

3Reliability

If the circuit pattern extends to the edge of the base plate, then electrical connectivity is maximized, but cracks may occur in the ceramic plate during repeated heat cycling

Engineering Contradiction:
Improveelectrical connectivityVSAvoidcrack resistance of base plate
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies preliminary action by designing the circuit pattern with a predetermined distance from the edge of the resin base plate before assembly and heat cycling occur. This pre-planned spacing creates a buffer zone that prevents stress concentration at the edges during subsequent thermal cycles, thereby preventing crack formation while maintaining adequate electrical connectivity through the circuit pattern design.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces warping and maintains heat dissipation performance, enhancing the long-term reliability of the semiconductor device by ensuring effective heat transfer and insulation.

Implementation Method 1

differences in thermal expansion coefficient between the ceramic plate and the circuit pattern and between the ceramic plate and the metal plate. Therefore, the insulated circuit substrate is warped by heat generated by the semiconductor chips

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

a sealing material which covers the insulated circuit substrate and the semiconductor chip and is surrounded by the case

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Implementation Method 3

reduces warping and maintains heat dissipation performance, enhancing the long-term reliability of the semiconductor device by ensuring effective heat transfer and insulation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20260060115A1Semiconductor device
Publication Date: 2026.02.26 FUJI ELECTRIC CO LTD
  • US20260060115A1 patent drawing
  • US20260060115A1 patent drawing
  • US20260060115A1 patent drawing

AI summary

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.