Circuit System Synchronous Error Detection and Scan Dump
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Solution Overview
Problem
Conventional chip testing methods face inefficiencies due to a time lag between detecting manufacturing defects and activating the scan chain to read register values, making it difficult to determine the cause of errors effectively.
Innovation Solution
A circuit system comprising two identical circuits and a comparator that synchronously perform testing operations, comparing intermediate signals in real-time to detect errors, and immediately initiating a scan dump operation to record transmission signals when differences are found, allowing for real-time data capture of error conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a scan chain is used to read out register values after detecting a chip error, then the error can be analyzed, but the time lag between error detection and scan chain activation causes the readout values to be outdated and ineffective for determining the cause of the error
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple scan chains (first scan chain and second scan chain) that are ready to immediately capture and hold register values at the moment of error detection. The scan chains are activated synchronously with the error detection event, eliminating the time lag by having the capture mechanism already in place and ready to act instantaneously when the error is detected.
2Productivity
If conventional testing methods are used with a single scan chain, then the testing process is simple, but the testing efficiency is low due to the time lag and inability to capture real-time error data
Solution Approach 1:
The patent applies segmentation by dividing the single scan chain into multiple separate scan chains (first scan chain and second scan chain), each capable of independently capturing and holding register values. This segmentation allows parallel operation of multiple scan chains, enabling simultaneous capture of error data from different time points or different error conditions, thereby improving testing efficiency without requiring a completely new testing system architecture.
3Reliability
If the scan chain is activated after a time lag to read out register values, then the testing process can be completed, but the captured values do not reflect the actual state at the time of error occurrence
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple scan chains (first scan chain and second scan chain) that are ready to immediately capture and hold register values at the moment of error detection. The scan chains are activated synchronously with the error detection event, eliminating the time lag by having the capture mechanism already in place and ready to act instantaneously when the error is detected.
Data Source
AI summary
A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.