Circular Pipeline Buffering for Idle-Free TCC Decoding
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Solution Overview
Problem
The computational intensity and resource requirements of Turbo Convolution Code (TCC) decoders in HSPA+ systems lead to inefficiencies due to idle processing cycles and high memory demands, particularly in parallel processing architectures where contention for data access occurs, making it difficult to achieve 100% utilization of processing units.
Innovation Solution
A circular pipeline processing system is implemented, where each processing stage includes a memory buffer and processing units configured to perform SISO operations in a circular pipeline, allowing for continuous processing of data blocks without idle cycles by selecting between unprocessed and partially processed blocks based on memory availability, and using either centralized or distributed memory architectures to manage data flow efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units are used to process data blocks in parallel, then throughput is increased, but memory requirements increase significantly
Solution Approach 1:
The system segments the processing of data blocks across multiple processing units in a circular pipeline, where each processing unit handles a subset of iterations for multiple data blocks. This segmentation allows parallel processing to increase throughput while reducing the memory burden on each individual processing unit, as each unit only needs to buffer a portion of the data blocks rather than all blocks required for full parallel operation.
2Productivity
If data blocks are divided across multiple processing units, then parallel processing is enabled, but contention for data access occurs
Solution Approach 1:
The system performs preliminary organization of data blocks in a circular buffer structure before processing begins. Each processing unit is pre-assigned specific data blocks and iteration ranges, establishing clear access patterns that eliminate contention. The circular pipeline architecture pre-positions data in memory locations that correspond to the processing sequence, ensuring that multiple processing units can operate in parallel without conflicting for data access.
3Device complexity
If a single processing unit performs consecutive SISO operations, then resource utilization is simplified, but idle cycles occur during write back
Solution Approach 1:
The circular pipeline architecture ensures continuity of useful action by having multiple processing units operate in a continuous cycle. While one processing unit is performing SISO operations on a data block, another processing unit simultaneously performs write back of extrinsic data for a different data block. This overlapping of operations eliminates idle cycles and maintains continuous productive work across the processing system, as each processing unit always has work available from the circular buffer.
4Productivity
If buffering two blocks is implemented for each processing unit, then idle cycles are avoided, but storage requirement doubles the maximum block size
Solution Approach 1:
The circular buffer structure implements a universal memory architecture that serves multiple processing units simultaneously. A single circular buffer of size equal to the maximum block size is shared across all processing units, with each unit accessing different portions of the buffer at different times. This multi-functional use of the same memory resource allows the system to eliminate idle cycles and support parallel processing without requiring each processing unit to have dedicated dual-block buffers, thereby reducing overall storage requirements while maintaining continuous operation.
Data Source
AI summary
In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.