Isolation Structure for CMOS Image Sensor Package Connections

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Solution Overview

Problem

Conventional CMOS image sensor chip scale packages face reliability issues due to exposed T-shaped connections being vulnerable to corrosion and peeling from moisture penetration, leading to failures in high temperature/high humidity tests.

Innovation Solution

An isolation structure is applied to the exposed connections by filling a trench created during the dicing process, using materials like epoxy, polyimide, or silicon nitride, which are co-planed with the cutting edge to prevent moisture damage, and are applied through methods such as chemical vapor deposition or physical vapor deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the wafer assembly is diced to separate individual packages, then the chip scale packages can be individually used and mounted, but the T-shaped connections become exposed and vulnerable to moisture penetration causing corrosion and peeling

Engineering Contradiction:
ImproveIndividual package usabilityVSAvoidConnection reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The substrate is segmented by dicing into individual chip scale packages while maintaining the T-shaped connections within each package. The isolation structure is also segmented to cover only the exposed connection areas at the cutting edges, allowing individual package usage while protecting vulnerable connections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An isolation structure acts as an intermediary element between the exposed T-shaped connections and the external environment. This isolation structure, made of moisture-blocking material, mediates the protection by preventing moisture penetration to the vulnerable connection areas while allowing the package to function normally.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the T-shaped connections are protected by a passivation layer during wafer fabrication, then the connections are protected during manufacturing, but the passivation layer does not extend to protect the exposed connection ends after dicing

Engineering Contradiction:
ImproveManufacturing process simplicityVSAvoidMoisture penetration
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The passivation layer is applied preliminarily during the wafer fabrication process to protect T-shaped connections before dicing. Additionally, an isolation structure is applied after dicing to extend protection to the previously unprotected exposed connection ends, ensuring continuous protection throughout the product lifecycle.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structure is applied locally only at the cutting edges where connections are exposed, rather than covering the entire substrate. This localized approach protects vulnerable areas while maintaining manufacturing efficiency and avoiding unnecessary material usage on already-protected areas.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The isolation structure effectively prevents corrosion and peeling of exposed connections, enhancing the reliability of CMOS image sensor chip scale packages by protecting them from moisture penetration, thereby ensuring they pass rigorous reliability tests.

Implementation Method 1

applied through methods such as chemical vapor deposition or physical vapor deposition

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 2

applied through methods such as chemical vapor deposition or physical vapor deposition

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS7833810B2Method of fabricating isolation structures for CMOS image sensor chip scale packages
Publication Date: 2010.11.16 VISERA TECH CO LTD
  • US7833810B2 patent drawing
  • US7833810B2 patent drawing
  • US7833810B2 patent drawing

AI summary

Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.