CIS Chip Package Structure Without Dam Sealing Contamination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip package structures, such as CMOS image sensor (CIS) chip packages, face issues with dam sealing techniques causing contamination of photosensitive areas and high costs associated with through-silicon via (TSV) techniques, which complicate processing and increase costs.
Innovation Solution
A chip package structure and manufacturing method that includes a protective or light transmitting layer on the photosensitive area of the chip to prevent EMC material overflow during molding, eliminating the need for dam sealing and simplifying the process, while using a molding layer with conductive vias and redistribution layers for fan-out connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dam sealing technique is used to prevent EMC material overflow, then the photosensitive area is protected from contamination, but the sealant easily overflows and pollutes the photosensitive area
Solution Approach 1:
A protective layer is formed on the photosensitive area before the molding process to prevent EMC material contamination. This preliminary protective measure eliminates the need for dam sealing techniques, as the protective layer acts as a barrier that prevents sealant overflow from reaching the photosensitive area during the molding process.
2Adaptability or versatility
If through-silicon via (TSV) technique is used to achieve fan-out connectivity, then connectivity is improved, but processing difficulty and cost increase
Solution Approach 1:
Instead of creating complex through-silicon vias through the chip substrate to achieve fan-out connectivity, the patent inverts the approach by forming the molding layer to extend over the photosensitive area and using redistribution layers on the molding layer surface. This alternative routing method achieves the same fan-out connectivity function while avoiding the complex TSV processing steps, thereby reducing manufacturing difficulty and cost.
Data Source
AI summary
A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a substrate; a chip spaced from the substrate and having a first surface, a second surface and a side surface, the first surface of the chip including a photosensitive area and a non-photosensitive area surrounding the photosensitive area; a molding layer having a first surface and a second surface, the molding layer provided on the non-photosensitive area of the chip and the side surface of the chip.