Semiconductor Cladding Layer Etching for Sub-3 nm Top Flatness
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Solution Overview
Problem
In contemporary semiconductor device fabrication, achieving a flat top surface for the cladding layer in non-planar transistor devices is challenging, which affects the processing window and increases costs and time in the fabrication process.
Innovation Solution
A method involving a sequential combination of two etching processes is used to pattern the cladding layer. The first etching process uses a wet etchant containing hydrofluoric acid and liquid ozone, while the second etching process uses a wet etchant containing ammonium and hydrogen peroxide, resulting in a vertical difference of less than 3 nanometers between the highest and lowest points of the cladding layer's top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single etching process is used to pattern the cladding layer, then the fabrication process is simpler and faster, but the top surface flatness deteriorates (vertical difference exceeds 3 nanometers)
Solution Approach 1:
The single etching process is divided into two sequential etching processes. The first etching process uses a first wet etchant to selectively remove portions of the cladding layer, and the second etching process uses a second wet etchant to further pattern the cladding layer. This segmentation allows each process to be optimized for specific aspects of pattern formation, achieving a vertical difference of less than 3 nanometers while maintaining reasonable process complexity.
Solution Approach 2:
Different parameters are used for the two etching processes, including different wet etchant compositions, different etching conditions, and different selectivity ratios. The first wet etchant has different chemical properties than the second wet etchant, allowing tailored control over the etching rate and selectivity at different stages of cladding layer patterning, thereby achieving the required flatness.
2Reliability
If the cladding layer is not properly patterned with flat top surface, then the fabrication process is shorter, but the processing window for subsequent steps is reduced
Solution Approach 1:
The cladding layer is patterned in advance with the two sequential etching processes to achieve a flat top surface before subsequent fabrication steps. This preliminary action ensures that the processing window for later steps (such as gate formation and contact alignment) is maximized, preventing compounding of alignment errors and yield loss in multi-step processes.
3Manufacturing precision
If conventional etching methods are used, then the fabrication cost is lower, but the vertical difference of the cladding layer top surface increases
Solution Approach 1:
The patent employs two different wet etchants with distinct chemical compositions and etching parameters. The first wet etchant is optimized for initial cladding layer removal, while the second wet etchant is optimized for fine-tuning the pattern and achieving the final flat top surface. This parameter optimization allows achieving superior vertical flatness without requiring expensive additional equipment or complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the processing window for the removal of the cladding layer, reducing the overall fabrication costs and time, while maintaining the performance of non-planar transistor devices.
Implementation Method 1
The first etching process uses a wet etchant containing hydrofluoric acid and liquid ozone
Implementation Method 2
The second etching process uses a wet etchant containing ammonium and hydrogen peroxide
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.