Differential Class AB Amplifier Biasing for Quiescent Current Matching
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Solution Overview
Problem
Class AB amplifiers face performance degradation due to mismatched quiescent currents in push and pull devices, leading to increased common mode and differential mode DC offsets, which affect distortion and power efficiency.
Innovation Solution
A differential amplifier circuit with a bias circuit that provides equal quiescent currents to push and pull transistors, and a voltage common mode feedback loop to correct common mode voltage, ensuring accurate quiescent current levels and reducing DC offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage biasing is used to set quiescent currents in push and pull devices, then the amplifier can operate as Class AB with reduced cross-over distortion, but the quiescent currents become mismatched due to process, temperature, and power-supply variations, leading to increased common mode and differential mode DC offsets
Solution Approach 1:
The patent employs a feedback mechanism where the quiescent currents of the push and pull devices are sensed and fed back to a control circuit. This control circuit adjusts the bias voltages to equalize the quiescent currents, compensating for variations due to process, temperature, and power-supply conditions. The feedback loop continuously monitors and corrects current mismatches, ensuring accurate current matching while maintaining Class AB operation with reduced cross-over distortion.
Solution Approach 2:
The amplifier circuit performs self-adjustment of its quiescent currents through an integrated control mechanism. The circuit automatically detects current mismatches between push and pull devices and self-corrects by adjusting bias conditions, eliminating the need for external calibration or manual adjustment. This self-service capability ensures continuous accurate current matching under varying operating conditions.
2Use of energy by moving object
If Class AB amplifier operation is implemented with push and pull devices, then power consumption is reduced compared to Class A, but quiescent currents flow through both devices causing increased power consumption and potential DC offset issues
Solution Approach 1:
The patent uses a feedback control system that monitors the quiescent currents flowing through the push and pull devices and adjusts bias voltages to equalize these currents. By ensuring matched quiescent currents, the feedback mechanism minimizes differential mode DC offsets at the output while maintaining the power-efficient Class AB operation mode. The system dynamically balances current distribution to prevent harmful DC offset accumulation.
3Loss of energy
If the quiescent currents through push and pull devices are not equal, then the amplifier can operate with lower power consumption, but the mismatched currents lead to circuit performance degradation such as increased common mode DC offsets
Solution Approach 1:
The patent implements a feedback control mechanism that senses quiescent current mismatches and adjusts bias conditions to equalize currents through push and pull devices. This feedback system maintains optimal current balance for high circuit performance while allowing the amplifier to operate in power-efficient Class AB mode. The continuous monitoring and adjustment ensure that power efficiency and performance reliability are both optimized simultaneously.
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AI summary
A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.