Clock Aligning Circuit Using a Single Global Chiplet Clock
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Solution Overview
Problem
In 2.5D/3D IC die-to-die interfaces, clock synchronization between chiplets is unsynchronized, requiring complex circuits that are not cost-effective for slower speed per link applications, especially in smaller pitch integrations.
Innovation Solution
A clock aligning circuit using a redistribution structure, phase align elements, and phase locked loops (PLLs) synchronizes chiplets with a single global clock, minimizing design changes and eliminating the need for complex circuits by using a simple circuit for smaller pitch integrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex circuit interface (e.g., UCIe) is used for clock synchronization, then synchronization reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the clock signal transmission with the existing data transmission infrastructure by routing the clock signal through the same redistribution structure and interconnects used for data, eliminating the need for separate dedicated clock distribution circuits and reducing overall system complexity
Solution Approach 2:
The redistribution structure is designed to serve multiple functions: it simultaneously transmits both data signals and clock signals between chiplets, replacing the need for separate dedicated structures for each signal type and simplifying the overall interface design
2Device complexity
If a simple circuit interface is used for smaller pitch integrations, then device complexity is reduced, but clock synchronization becomes difficult
Solution Approach 1:
The patent introduces a phase alignment mechanism that acts as an intermediary between the simple circuit interface and the clock synchronization requirement, adjusting phase differences caused by varying path lengths without adding complex circuitry
Solution Approach 2:
The system dynamically adjusts timing parameters by allowing different chiplets to operate with phase-offset clocks, where the phase relationship is controlled and coordinated through a master-slave configuration rather than requiring absolute synchronization
3Reliability
If separate clock signals are transmitted to each chiplet, then clock alignment is improved, but bandwidth and power efficiency decrease
Solution Approach 1:
The patent combines multiple clock signals into a single shared clock distribution network that serves all chiplets, reducing the total number of clock signals transmitted and thereby lowering power consumption while maintaining synchronization through coordinated phase management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves cost-effective clock synchronization across chiplets, reducing the need for complex circuits and enhancing bandwidth and power efficiency in smaller pitch integrations.
Implementation Method 1
a second phase locked loop (PLL) of the second chiplet to align a phase of the clock signal from the first chiplet with a local phase locked loop (PLL) clock
Data Source
AI summary
A semiconductor package includes a plurality of semiconductor chips. The semiconductor package includes a redistribution structure. The redistribution structure can be configured to electrically couple the plurality of semiconductor chips to each other, and further configured to transmit a single global clock signal. Data transferred across the plurality of semiconductor chips can be synchronized in a clock domain to which the single global clock signal belongs.