Clock Oscillator Amplitude Control to Prevent Transistor Breakdown
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Solution Overview
Problem
Existing clock signal generating circuits face challenges in adjusting the amplitude of clock signals to prevent transistor damage while maintaining an improved signal-to-noise ratio, as excessive amplitude increase can lead to transistor breakdown.
Innovation Solution
A clock signal generating circuit that includes a detecting circuit to generate a voltage based on clock signals and setup voltages, a comparing circuit to output a check signal for modulation operations, and an oscillator to adjust the amplitude of clock signals using a control code, thereby limiting the amplitude and preventing transistor damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amplitude of the clock signal is increased to improve the signal-to-noise ratio, then the performance of the oscillator is improved, but the transistors configuring the oscillator may be damaged
Solution Approach 1:
The patent introduces an amplitude adjustment circuit as an intermediary component between the oscillator and the output. This circuit includes a detecting circuit that generates a voltage based on the clock signal amplitude, a comparing circuit that compares this voltage with a reference voltage, and a code generating circuit that produces a control code based on the comparison result. This control code then adjusts the amplitude of the clock signal to prevent excessive amplitude that could damage transistors, while still maintaining sufficient amplitude for good signal-to-noise ratio.
Solution Approach 2:
The patent implements a feedback mechanism where the amplitude of the clock signal is continuously monitored by the detecting circuit, which generates a voltage proportional to the amplitude. This voltage is compared with a reference voltage by the comparing circuit, and the comparison result feeds back to the code generating circuit to adjust the amplitude control. This closed-loop feedback system ensures the amplitude remains within safe limits while optimizing signal quality.
Data Source
AI summary
A clock signal generating circuit includes a detecting circuit configured to generate a first voltage based on first and second clock signals and adjust a level of the first voltage in response to first and second setup voltages and a resistance variable code, a comparing circuit configured to compare the first voltage and a reference voltage and output a check signal according to a comparison result, a code generating circuit configured to perform a first modulation operation for determining the resistance variable code in response to the check signal and perform a second modulation operation for determining a control code in response to the check signal, and an oscillator configured to adjust an amplitude of the first and second clock signals in response to the control code, and output the first and second clock signals having the adjusted amplitude.