Multiphase Clock Buffer Chain for Duty Cycle and Phase Skew Correction
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Phase-Locked Loops (PLL) and Delay-Locked Loops (DLL) struggle to maintain stable and accurately phased receiver clock signals due to variations among ring oscillator elements, leading to undesirable duty cycle variations and skew between output clock phases.
Innovation Solution
A configurable clock buffer chain is employed, allowing adjustment of clock duty cycle and delay by modifying the rise and fall times of signals between buffer stages, combined with a measurement subsystem to directly measure and correct clock duty cycle and inter-phase skew, providing clean, accurately timed multiphase clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL or DLL is used to generate multiple local clock phases, then the desired frequency and phase relationship is achieved, but variations among ring oscillator elements induce periodic clock variations resulting in undesirable duty cycle variations and skew between output clock phases
Solution Approach 1:
The patent introduces an intermediary measurement subsystem that directly measures the actual duty cycle and skew of generated clock signals. This measurement subsystem acts as a mediator between the clock generation system and the final output, detecting deviations and enabling correction through feedback control, thereby resolving the contradiction between achieving desired phase relationships and maintaining manufacturing precision
Solution Approach 2:
The patent implements feedback control by continuously measuring clock duty cycle and skew using the measurement subsystem and using these measurements to adjust the clock generation process. The feedback loop compensates for variations among ring oscillator elements, maintaining reliable clock signal generation while correcting duty cycle inaccuracies that would otherwise result from manufacturing variations
2Reliability
If a PLL or DLL is used to generate multiple local clock phases, then the desired frequency and phase relationship is achieved, but variations among ring oscillator elements induce periodic clock variations resulting in skew between output clock phases
Solution Approach 1:
The measurement subsystem serves as an intermediary that directly measures inter-phase skew between output clock phases. By introducing this measurement capability, the system can detect phase alignment errors caused by ring oscillator variations and enable corrective action, thus maintaining reliability while improving phase alignment precision
Solution Approach 2:
The feedback mechanism uses direct measurements of inter-phase skew to adjust the clock generation process. This feedback loop compensates for manufacturing variations in ring oscillator elements, ensuring that multiple local clock phases maintain accurate phase relationships despite inherent component variations
3Manufacturing precision
If a configurable clock buffer chain is used to adjust duty cycle and delay, then clean and accurately timed multiphase clock signals are produced, but the device complexity increases
Solution Approach 1:
The configurable clock buffer chain is designed to perform multiple functions: adjusting duty cycle, controlling delay, and generating multiphase clock signals. By making the buffer chain universal and multi-functional, the patent achieves high clock signal accuracy without proportionally increasing device complexity, as a single configurable structure handles multiple correction and generation tasks
Data Source
AI summary
Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.