Clock Buffer Topology With Source Degeneration for Noise Immunity
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Solution Overview
Problem
Conventional clock buffer circuits are susceptible to noise from the power supply and ground nodes, which degrades the integrity of the delayed clock signal.
Innovation Solution
A clock buffer circuit design that incorporates a first and second inverter with PMOS and NMOS transistors, connected to source nodes via resistors, providing source degeneration to alleviate noise immunity, and configured in a differential topology to reduce common-mode disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cascade inverter topology is used, then circuit simplicity is maintained, but noise immunity deteriorates due to susceptibility to power supply and ground node noises
Solution Approach 1:
The clock buffer circuit is segmented into multiple independent inverter stages (first inverter, second inverter) with separate power supply connections. Each inverter stage has its own power pin connected to VDD and ground pin connected to VSS, isolating the noise paths between stages and preventing noise propagation through shared power/ground nodes.
Solution Approach 2:
The patent introduces intermediate buffering stages between the input and output clock signals. These intermediate inverters act as mediators that regenerate and clean the clock signal, blocking noise from propagating from the power supply and ground nodes to the output while maintaining signal integrity.
2Reliability
If standard inverter configuration is used, then manufacturing simplicity is maintained, but signal integrity deteriorates due to transistor-induced noise
Solution Approach 1:
The circuit is divided into multiple discrete inverter stages rather than using a single complex gate. Each inverter stage is a simple, well-established circuit block that is easy to manufacture with standard CMOS processes, while the multi-stage architecture collectively achieves superior signal integrity by isolating noise sources.
Solution Approach 2:
The patent acknowledges that transistors inherently generate noise, but converts this challenge into a benefit by using multiple transistor stages. Each stage's noise is isolated and does not accumulate, while the stages collectively provide signal regeneration and noise filtering, turning the noise-generating transistors into noise-isolating building blocks.
Data Source
AI summary
An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node.