Clock Buffer Circuit with Node Voltage Control for Noise Margin
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Solution Overview
Problem
Semiconductor apparatuses face challenges in maintaining sufficient signal determination margins as clock frequencies increase, leading to potential malfunctions due to noise generated when signals are not toggled.
Innovation Solution
A semiconductor apparatus is designed with a node voltage control circuit to generate a node voltage code based on a control code, a first buffer to create preliminary clocks and clock bars from an external clock, and a second buffer to amplify and delay these signals, thereby increasing signal determination margins and preventing noise-induced malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to achieve higher processing speeds, then the productivity is improved, but the signal determination margin becomes insufficient leading to malfunctions
Solution Approach 1:
The patent applies preliminary action by generating preliminary clocks and preliminary clock bars in advance through the first buffer circuit, and then using these pre-prepared signals as inputs for the second buffer circuit. This preliminary preparation ensures that valid signal levels are established before the main clock edges arrive, thereby maintaining sufficient determination margins even at high clock frequencies.
Solution Approach 2:
The patent introduces preliminary clocks and preliminary clock bars as intermediary signals between the external clock and the internal logic circuits. These intermediary signals serve as buffer elements that transition the high-frequency external clock into controlled intermediate signals with proper voltage levels, preventing direct noise coupling while maintaining timing relationships.
2Productivity
If the clock frequency is increased, then the productivity is improved, but noise is generated when signals are not toggled causing malfunctions
Solution Approach 1:
The preliminary clocks and preliminary clock bars act as intermediary signals that isolate the external clock from internal circuits. By using these intermediate signals with controlled voltage levels, the patent prevents noise generated by direct clock toggling from coupling into the internal logic, while still allowing high-frequency operation.
Solution Approach 2:
The patent applies beforehand cushioning by establishing preliminary signal levels through the first buffer circuit before the main clock edges are processed. This preliminary buffering creates a cushion of stable voltage levels that absorbs and dampens noise spikes, preventing them from propagating through the circuit and causing malfunctions.
3Device complexity
If a single buffer is used to generate preliminary clocks, then the device complexity is reduced, but the signal determination margin is insufficient
Solution Approach 1:
The patent applies segmentation by dividing the clock buffering function into two separate buffer circuits. The first buffer generates preliminary clocks and preliminary clock bars, while the second buffer processes these preliminary signals into final internal clocks. This segmentation allows each buffer to be optimized for its specific function, ensuring sufficient determination margins while maintaining manageable overall complexity.
Data Source
AI summary
A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.