Clock Buffer Voltage Control for High-Frequency Signal Margins

Solution Overview

Problem

Semiconductor apparatuses face challenges in maintaining sufficient signal determination margins as clock frequencies increase, leading to potential malfunctions due to noise generated when signals are not toggled.

Innovation Solution

A semiconductor apparatus is designed with a node voltage control circuit to generate a node voltage code based on a control code, a first buffer to create preliminary clocks and clock bars from an external clock, and a second buffer to amplify and delay these signals, effectively managing voltage levels and delay times to prevent noise-induced malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the clock frequency is increased to achieve higher processing speed, then the productivity is improved, but the signal determination margin becomes insufficient leading to malfunctions

Engineering Contradiction:

Improveprocessing speedVSAvoidsignal determination margin

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by generating preliminary clocks and preliminary clock bars in advance through the first buffer before the main clock signal is needed for determination. This preliminary generation allows the system to prepare timing signals ahead of time, ensuring sufficient determination margins even at high clock frequencies. The preliminary clocks are generated based on external clocks and node voltage codes, creating a buffer of pre-prepared timing signals that prevent malfunctions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism through the introduction of preliminary clocks and preliminary clock bars that mediate between the external clock and the internal signal determination process. These preliminary clocks act as intermediate signals that bridge the timing gap, allowing the system to maintain reliable signal determination at high frequencies by providing an intermediate timing reference that is less susceptible to noise and timing violations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the clock frequency is increased to achieve higher processing speed, then the productivity is improved, but noise is generated when signals are not toggled causing malfunctions

Engineering Contradiction:

Improveprocessing speedVSAvoidnoise

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by generating preliminary clocks and preliminary clock bars in advance through the first buffer before the main clock signal is needed for determination. This preliminary generation allows the system to prepare timing signals ahead of time, ensuring sufficient determination margins even at high clock frequencies. The preliminary clocks are generated based on external clocks and node voltage codes, creating a buffer of pre-prepared timing signals that prevent malfunctions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism through the introduction of preliminary clocks and preliminary clock bars that mediate between the external clock and the internal signal determination process. These preliminary clocks act as intermediate signals that bridge the timing gap, allowing the system to maintain reliable signal determination at high frequencies by providing an intermediate timing reference that is less susceptible to noise and timing violations.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If voltage levels are not controlled at high frequencies, then the device complexity is reduced, but phase changes occur causing malfunctions

Engineering Contradiction:

Improvevoltage control mechanismVSAvoidphase stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies preliminary action by generating preliminary clocks and preliminary clock bars in advance through the first buffer before the main clock signal is needed for determination. This preliminary generation allows the system to prepare timing signals ahead of time, ensuring sufficient determination margins even at high clock frequencies. The preliminary clocks are generated based on external clocks and node voltage codes, creating a buffer of pre-prepared timing signals that prevent malfunctions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting node voltage levels based on detected voltage conditions. The node voltage control circuit monitors voltage at specific nodes and adjusts voltage codes to maintain optimal voltage levels during high-frequency operation. This dynamic parameter adjustment prevents phase changes and signal integrity issues that would otherwise occur at high frequencies, ensuring reliable operation without requiring overly complex control mechanisms.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10862478B2Semiconductor device and system including the same

Publication Date: 2020.12.08 SK HYNIX INC

AI summary

A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.