Analog Frequency-Locked Clock Circuit for PVT-Stable Output
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Solution Overview
Problem
Existing clock circuits in microcontroller units (MCUs) and microprocessor units (MPUs) are affected by variations in process, voltage, and temperature, leading to inconsistent frequency output.
Innovation Solution
A clock circuit design incorporating a reference and feedback branch with variable capacitors and resistors, along with dividers and an amplifier, forms an analog frequency lock loop to stabilize the output frequency, compensating for these variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable clock circuit is used to generate various frequencies, then frequency versatility is improved, but frequency accuracy deteriorates due to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a phase-locked loop (PLL) feedback mechanism where the output clock signal is fed back through a feedback divider to a phase detector that compares it with the reference clock signal. This closed-loop feedback system continuously adjusts the VCO frequency to maintain accurate output despite PVT variations, resolving the contradiction between frequency versatility and frequency accuracy
Solution Approach 2:
The patent uses programmable dividers (feedback divider and reference divider) that can change their division ratios dynamically. By adjusting these parameter settings, the circuit can generate various output frequencies while the PLL feedback mechanism ensures accuracy is maintained for each programmed frequency, thus achieving both versatility and accuracy
2Device complexity
If simple clock generation is used, then device complexity is reduced, but frequency stability deteriorates under process, voltage, and temperature variations
Solution Approach 1:
The phase-locked loop provides automatic frequency stabilization through feedback control. The phase detector generates error signals that adjust the VCO to compensate for PVT variations, achieving frequency stability without requiring complex external stabilization circuits
Solution Approach 2:
The patent combines multiple functions into integrated blocks: the phase detector merges reference clock comparison and error signal generation; the charge pump combines current sourcing and sinking; the loop filter integrates filtering and DC blocking. This functional integration achieves frequency stability while managing circuit complexity through consolidation
Data Source
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AI summary
A clock circuit comprising a voltage-controlled oscillator having an input coupled to an output of an amplifier, and an output, outputting an output clock signal. The clock circuit further comprises, a reference branch and a feedback branch, both comprising, a first switch coupled to an input via an inverter and a second switch coupled to the input. The branches also both comprise, a variable capacitor coupled to a reference potential and coupled to the first switch, and a variable resistor coupled to the first switch. Both branches comprise a supply voltage coupled to the variable resistor and an output node, wherein the second switch is coupled to the variable capacitor and coupled to a node. The reference branch input is an input clock signal and the output is a reference voltage, and the feedback branch input is an output clock signal and the output is a feedback voltage.