Clock Control Circuitry for Dynamic Test Pulse Selection
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Solution Overview
Problem
Existing methods for marginal defect testing of integrated circuits are inefficient, particularly when testing logic circuits that require different clock polarities, as they often necessitate using three at-speed clock pulses for all circuits, even if only two are necessary, which can miss defects that appear at normal operating frequencies.
Innovation Solution
The implementation of clock control circuitry that includes a multiplexer and burst counter to generate and manage default one and zero clock signals based on a clock polarity control signal, allowing for independent testing of IP blocks with varying clock polarity requirements using either one or two clock pulses, thereby enhancing test efficiency and defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three at-speed clock pulses are used for all logic circuits, then all logic circuits can be tested, but testing efficiency is reduced and test time is prolonged
Solution Approach 1:
The patent implements dynamic clock pulse generation where the number of clock pulses (one or two) is dynamically selected based on the specific IP block being tested and its clock polarity requirements. The clock control circuitry switches between different clock pulse configurations to match the test requirements of each IP block, rather than using a fixed three-pulse sequence for all blocks.
Solution Approach 2:
The patent changes the parameters of the clock signal (number of pulses, polarity) based on the specific IP block being tested. The clock control circuitry receives control signals that determine the clock polarity and pulse count, allowing the testing system to adapt the clock parameters to match each IP block's requirements, thereby reducing test time while maintaining defect detection coverage.
2Reliability
If three at-speed clock pulses are used for all logic circuits, then comprehensive testing is achieved, but adaptability to different clock polarity requirements is reduced
Solution Approach 1:
The system dynamically adjusts the clock polarity and pulse count based on the specific IP block requirements. The clock control circuitry receives control signals that determine whether to generate positive or negative polarity clock pulses, and whether to use one or two pulses, thereby adapting to different clock polarity requirements of various IP blocks.
Solution Approach 2:
The clock control circuitry serves multiple functions: it generates both positive and negative polarity clock signals, controls the number of clock pulses (one or two), and adapts to different IP block requirements. This multi-functional approach allows a single testing system to handle diverse clock polarity requirements without requiring separate testing circuits for each IP block type.
3Ease of operation
If fixed clock pulse sequences are used, then circuit operation is simplified, but testing efficiency for different IP blocks is reduced
Solution Approach 1:
The clock control circuitry acts as an intermediary between the test controller and the IP blocks. It receives control signals from the test controller and generates the appropriate clock signals (with correct polarity and pulse count) for each IP block. This intermediary layer maintains simple IP block operation while enabling efficient, adapted testing for different blocks.
Data Source
AI summary
A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.