Clock Control for Pipelined Memory Delay Fault Testing
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Solution Overview
Problem
Testing pipelined memory arrays in integrated circuits is complex due to their read latency, which makes cycle-by-cycle delay fault testing using ATPG methods unreliable, leading to spurious data and reduced test coverage.
Innovation Solution
A method where the clock control signal manages the capture of data from pipelined memory banks in a scan-out chain, enabling or disabling the clocking of these banks to prevent spurious data capture and allow for valid data to be obtained after the read latency period, thereby enhancing test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cycle-by-cycle delay fault testing is performed using ATPG methods on pipelined memory arrays, then test coverage is attempted, but spurious data is captured due to read latency causing reduced test coverage
Solution Approach 1:
The patent applies preliminary action by disabling the clock signal to the pipelined memory array before capturing test data. This preliminary disabling prevents the memory from updating its internal state during the capture window, ensuring that only valid previously-loaded data is captured and eliminating spurious data caused by read latency. The clock is re-enabled after capture to restore normal operation.
Solution Approach 2:
The patent applies preliminary anti-action by using the clock disable signal to counteract the harmful effect of read latency. By disabling the clock in advance of data capture, the patent prevents the memory array from performing read operations that would otherwise cause spurious data to appear at the output, thereby eliminating the source of measurement error.
2Measurement precision
If the clock control signal disables clocking during data capture, then spurious data is prevented, but the testing process becomes more complex
Solution Approach 1:
The patent applies universality by using the existing clock control signal, already present in the pipelined memory array design for normal operation control, to also serve the additional function of data capture control during testing. This multi-functional use of the clock signal avoids adding separate control circuitry and minimizes testing process complexity while achieving precise data capture.
Solution Approach 2:
The patent applies self-service by utilizing the memory array's own clock control mechanism to solve the data capture problem. Rather than introducing external complex control logic, the existing clock infrastructure is repurposed to automatically prevent spurious data capture, making the testing process simpler and more integrated with the device's native control structures.
3Measurement precision
If read latency of pipelined memory is accounted for, then accurate data capture is achieved, but test setup complexity increases
Solution Approach 1:
The patent applies preliminary action by loading test data into the pipelined memory array in advance, before the actual delay fault testing begins. This preliminary data loading accounts for the read latency by ensuring that valid data is already present in the memory when the clock is disabled during capture, eliminating the need for complex real-time latency compensation circuitry.
Solution Approach 2:
The patent applies the intermediary principle by using the clock disable signal as a mediator between the test data loading process and the data capture process. This intermediary control signal coordinates the timing between these two operations, ensuring that data is captured only when valid data is present in the memory, thereby simplifying the overall test setup by providing a clear synchronization mechanism.
Data Source
AI summary
In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.