Electronic Circuit Testing TRIZ Cases
- Wafer Probe Alignment Control Using Historical Offset Correction
Automated wafer probe alignment system uses historical offset data to orient probe cards precisely against test pads.
- Programmable MBIST Controller for Flexible Memory Testing
A programmable MBIST controller applies dynamic test algorithms to embedded memories during manufacturing.
- CMOS FET Degradation Measurement via Segmented Ring Oscillator Stages
A segmented ring oscillator system measures individual transistor electrical properties to determine degradation levels.
- Cross-Configured Conductive Probe Tip for Semiconductor Inspection
A conductive probe features a cross-shaped tip with linear ridges and vertexes to establish electrical contact.
- Integrated Circuit Contact Resistance Measurement via Dual-Pin Current Analysis
A dual-pin testing method measures current through an integrated circuit to calculate contact resistance directly.
- Conforming Test Socket for Curved IC Devices
Compliant test sockets prevent permanent deformation of thin curved substrates by distributing pressure evenly across the device surface.
- Liquid Cooled Test Socket for Semiconductor IC Chips
A liquid cooled test socket submerges contacts in two phase fluid coolant to manage thermal loads during semiconductor integrated circuit chip testing.
- Exposed Redistribution Layer for Semiconductor Package Testing
Exposing redistribution layer portions via dielectric openings enables cost-effective testing before high-temperature encapsulation damages components.
- Prober Alignment Suppressing Abbe Error
Aligning the draw-out direction of the maintenance device with the conveyance direction of the object suppresses Abbe error during high-accuracy positioning.
- Transfer-Printable Micro-Device Testing via Separated Tethers
A source wafer structure connects micro-devices to test pads through removable electrical paths for pre-transfer functional verification.
- Analog Circuit Arrangement for Signal Testing
A circuit arrangement implements an alternative calculation rule to generate a test signal for error checking of analogue input signals.
- Probe Card Temperature Control for Contact Accuracy
A probe card uses a temperature-controlling unit to heat or cool the card within an allowable range, ensuring needle-to-pad contact.
- Touch Panel Metal Mesh Defect Detection via Capacitive Coupling
Capacitive coupling signal transceiving component identifies branch path defects in touch panel metal meshes, resolving low reliability and accuracy issues.
- Dual-Surface Electronic Device Testing Contact Arm Alignment
Segmented positioning systems align dual-surface electronic devices against sockets, reducing miss contacts and improving testing efficiency.
- Capacitive Sensors for Flip-Chip Package Reliability Monitoring
Capacitive sensors integrated into flip-chip packages detect mechanical stress and crack propagation through real-time capacitance changes.
- Crack Sensor Polymer Healing Layer Suppressing Crack Growth
A crack sensor employs a polymer layer that restores conductive cracks using restoring force, preventing sensitivity loss from repeated mechanical stress.
- Semiconductor Memory Calibration Circuit for Setup Hold Timing
Internal PRBS testing calibrates data strobe interlock delays to guarantee setup hold values across process voltage temperature variations.
- Scan Input Processing Circuit for Flip-Flop Testing
A scan input processing circuit routes signals to flip-flops using NAND and OAI gates.
- Pulsed Flip-Flop Scan Test Circuit for Hold Time Violations
A pulsed flip-flop design integrates scan test functionality using a multiplexer and modified latch structures.
- Per-Pin Scan Chain Diagnosis for Limited Failure Cycles
Per-pin diagnosis techniques isolate fault candidates within segmented scan chains to improve diagnostic resolution.
- Direct Contact Heating Element for Semiconductor Testing
A ceramic heating element provides direct mechanical contact with discrete semiconductor components for rapid thermal processing.
- Expectation Based Event Verification for Memory Agent Testing
A testing apparatus generates expected output signals from input data to verify memory agent operation through external signal comparison.
- AC Power Fault Detection Using Bandpass Filtering
Bandpass filters extract fundamental voltage components to identify phase failures quickly without complex real-time calculations.
- IC Test Controller Skipping Redundant Patterns
A test controller skips ineffective patterns using stored indications to feed only valid sequences.
- Test Tray Transfer Mechanism for Semiconductor Handlers
A single test tray transferring apparatus uses independently actuated gripping blocks to move transport containers along a circulation path.
- PCBA Non-Functional Area Destructive Testing
Applying accelerated stressors to non-functional PCB areas yields representative reliability data without destroying functional components.
- Sequential Semiconductor Tester Module Segmentation
Segmenting the tester into series-connected modules reduces manufacturing cost and complexity while maintaining signal integrity during high-speed testing.
- Inspection System Vertical Stacking Reduces Footprint
Stacking inspection units vertically and positioning the loader at one end reduces footprint area while maintaining alignment accuracy.
- Scannable Register File Architecture for Low-Overhead Memory Testing
A scannable register file uses a latch-based scan chain to shift test data through memory cells without internal BIST hardware.
- Current Sensor Malfunction Detection via Addition Difference Correlation
A dual sensor system computes addition and difference values to detect malfunctions through correlation analysis.
- SoC Design Verification Using Virtual Model and Registers
A verification system uses a virtual model to check direct connections between circuit blocks without physical prototypes.
- Test Carrier Flow Passage for DUT Thermal Management
A test carrier integrates a fluid flow passage to circulate cooling medium near the device under test.
- Parallel Signature Unit for Hardware Data Integrity Verification
A parallel signature unit accumulates processor memory values to verify data integrity without software overhead.
- Radiation-Resistant FPGA Circuit Design via Reference Mapping
A radiation-resistant FPGA circuit design method uses reference mapping to optimize element placement for enhanced robustness.
- Thermal Control Unit Evaporation Chamber Semiconductor Testing
Sealed evaporation chamber transfers heat from device under test to refrigerant, eliminating secondary cooling systems and reducing system complexity.
- Scan Test Circuit Mode Selection for Delay Fault Coverage
A scan test circuit selects between skewed-load and broadside modes to optimize delay fault coverage.
- Backward Propagation Test Case Generation for Floating Point Units
A test case generation method propagating predefined results backwards to control operand values.
- Shift Register Circuit Pulse Width Control for Threshold Compensation
A shift register circuit generates scan and emission signals with specific pulse widths to support pixel units.
- Semiconductor Memory Tester Frequency Division Timing
A semiconductor memory tester uses frequency division to generate timing signals from the device under test clock.
- Low Overdrive Probes with Compliant Substrate for Semiconductor Testing
Segmenting overdrive between low-overdrive probes and a compliant substrate resolves stress issues while maintaining signal integrity.
- Clock Control for Pipelined Memory Delay Fault Testing
Disabling the clock prevents spurious data from read latency, improving delay fault test coverage.
- Display Panel Test Pad Unit Disable Mechanism
Auxiliary pads stabilize disable voltage application across misaligned flexible circuit boards, reducing component size and manufacturing costs.
- Test Vehicle With Passive Dies For Solder Interconnect Reliability
Passive dies in the test vehicle enable parallel design and testing of chip packages, reducing manufacturing complexity.
- Conformable Test Fixture Head for Lid-Less IC Packages
Independently movable pushers in the test fixture head accommodate varying die heights, reducing stress on lid-less integrated circuit packages.
- DC Solenoid Plunger Detection via Current Sense Peak Valley Analysis
Detects DC solenoid plunger movement by comparing peak and valley coil currents to generate a level-shifted signal for position tracking.
- In-die Transistor Characterization via Integrated DAC and ADC
Integrated digital-to-analog and analog-to-digital converters enable on-die transistor characterization without external test interfaces.
- Display Device Delay Period for High-Resolution Data Writing
A display device sets a delay period after data signal output to ensure sufficient charging time in pixel circuits.
- Diagnostic Wafer for MRAM Magnetic Field Measurement
A diagnostic wafer with magnetization detection units measures magnetic fields applied to wafers under test.
- On-Die Aging Detector Circuit for Early Lifetime Failure Detection
Ring oscillator delay stages measure aging variability to detect latent reliability issues without static guard-banding.