Scan Input Processing Circuit for Flip-Flop Testing
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Solution Overview
Problem
As integrated circuits (ICs) with increasing memory storage capacity face higher manufacturing defects, existing scan chain technologies struggle to reliably test and maintain the integrity of flip-flops, leading to potential operational failures.
Innovation Solution
The implementation of a scanning circuit comprising a NAND gate, an OR-AND-INVERT (OAI) gate, and a flip-flop, which processes scan inputs and data inputs based on a scan enable signal to ensure secure setup and hold times during scan operations, minimizing layout area and enhancing operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory storage capacity is increased, then storage capability is improved, but manufacturing defects increase
Solution Approach 1:
The patent implements preliminary testing actions through scan chains that test flip-flops before final product completion. The scan enable signal activates test modes that verify storage elements in advance, allowing defects to be detected and addressed before the IC leaves the manufacturing process, thus maintaining reliability despite increased storage capacity.
Solution Approach 2:
The patent establishes feedback mechanisms where test results from scan chain operations are fed back to identify and isolate defective flip-flops. This feedback loop enables continuous verification and quality control, ensuring that increased memory capacity does not compromise overall product reliability through systematic defect detection and reporting.
2Reliability
If scan chain testing is implemented, then manufacturing defect detection is improved, but layout area increases
Solution Approach 1:
The patent merges the scan chain testing functionality with the existing flip-flop storage elements. By combining the test infrastructure with the functional storage elements, the layout area increase is minimized while still achieving comprehensive defect detection capability across all memory elements.
Solution Approach 2:
The patent designs flip-flops to serve dual purposes: normal operational storage and scan chain testing. The same storage elements are used for both data storage during normal operation and for testing during manufacturing verification, eliminating the need for separate dedicated test elements and reducing overall layout area requirements.
3Reliability
If scan input processing circuit is added, then scan input integrity is maintained, but device complexity increases
Solution Approach 1:
The patent introduces a scan input processing circuit that acts as an intermediary between the external scan input and the internal flip-flop storage elements. This intermediary circuit processes and conditions the scan input signals, ensuring integrity and proper timing while maintaining a clear separation between test infrastructure and functional logic, thus managing complexity systematically.
Data Source
AI summary
An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.