Display Device Delay Period for High-Resolution Data Writing

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Solution Overview

Problem

In organic EL display devices using the SSD method, data writing failures occur due to diode-connection issues, leading to insufficient charge of data voltage in pixel circuits, especially with the shortening of horizontal intervals in high-resolution displays, resulting in luminance unevenness and inability to express gray scales effectively.

Innovation Solution

A display device and driving method where a delay period is set after data signal output in each horizontal interval, allowing the scanning line to select corresponding pixel circuits only after the delay period ends, ensuring sufficient time for data signal writing and internal compensation, thereby preventing data writing failures and improving luminance uniformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the horizontal interval is shortened to achieve high resolution, then the display resolution is improved, but the data writing time is insufficient causing data writing failures

Engineering Contradiction:
Improvedisplay resolutionVSAvoiddata writing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent introduces a delay period before the scanning line selects pixel circuits, allowing data signals to be fully written to the pixel circuits before selection occurs. This preliminary action ensures that data writing is completed in advance, preventing data writing failures even when horizontal intervals are shortened for high resolution displays.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the scanning line selects pixel circuits immediately after data signal output, then the operation speed is improved, but data writing failures occur due to insufficient charging time

Engineering Contradiction:
Improveoperation speedVSAvoiddata writing reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The delay period is implemented as a preliminary action that ensures data signals are fully written and charged to pixel circuits before the scanning line performs selection. This maintains operational reliability by ensuring sufficient charging time while minimizing the delay to keep operation speed high.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent optimizes the delay period duration as a controllable parameter, balancing it to be long enough to ensure complete data writing and charging (improving reliability) but short enough to maintain high operation speed. This parameter adjustment resolves the contradiction between speed and reliability.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the data signal is written quickly to maintain high refresh rate, then the refresh rate is improved, but luminance unevenness occurs due to insufficient internal compensation

Engineering Contradiction:
Improverefresh rateVSAvoidluminance uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The delay period serves as a preliminary compensation phase where pixel circuits perform internal compensation operations before the scanning line selects them for display. This ensures that luminance uniformity is established in advance, allowing quick subsequent operations that maintain high refresh rates without sacrificing luminance precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10657893B2Display device
Publication Date: 2020.05.19 SHARP KK
  • US10657893B2 patent drawing
  • US10657893B2 patent drawing
  • US10657893B2 patent drawing

AI summary

The present application discloses a display device and a driving method thereof using the SSD method capable of charge with the data voltage in the pixel circuit and sufficient internal compensation even if the high resolution of a display image is improved.m demultiplexers corresponding to m sets of data signal line groups with k data signal lines being one set are provided. Each demultiplexer sets a prescribed period in a period after a time point when to start supplying a data signal output last in each of horizontal intervals among m data signals to a time point before a time point when to end supplying the data signal is set in advance as a delay period, and a scanning line drive circuit starts to select a scanning line corresponding to the pixel circuit to which the prescribed number of data signals are supplied, when the delay period of each of the horizontal intervals ends.