Scannable Register File Architecture for Low-Overhead Memory Testing
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Solution Overview
Problem
Conventional SRAM in ASICs and other circuits faces performance penalties and significant power consumption due to built-in self-test (BIST) circuitry, which also occupies substantial space.
Innovation Solution
A scannable register file (SRF) architecture with a scan chain of coupled latches, input and output logic, a scan clock generator, and an odd/even generator, utilizing multiplexers and control signals to enable efficient testing without the need for bulky BIST circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM with BIST circuitry is used, then testing capability is provided, but performance penalties occur due to multiplexers and comparators
Solution Approach 1:
The patent extracts and removes the bulky BIST circuitry (multiplexers, comparators, test logic) from the SRAM structure. Instead of building-in self-test capabilities that consume area and performance resources, the design uses external test equipment to apply scan sequences to the scan chain, eliminating the need for internal test hardware that causes performance penalties.
Solution Approach 2:
The scan chain latches serve dual functions: they function as normal memory storage elements during regular operation and as testable components when scan mode is activated. This multi-functionality allows the same hardware to perform both storage and testing without requiring separate dedicated test circuits, thereby improving performance while maintaining testing capability.
2Reliability
If conventional SRAM with BIST circuitry is used, then testing capability is provided, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive BIST circuitry from the SRAM structure. The extraction of test logic, multiplexers, and comparators eliminates the continuous power consumption associated with these components during normal operation, while still enabling testing through external scan sequence application to the scan chain.
3Reliability
If conventional SRAM with BIST circuitry is used, then testing capability is provided, but area footprint increases
Solution Approach 1:
The patent extracts and removes the bulky BIST circuitry including multiplexers, comparators, and test logic from the SRAM area. This extraction significantly reduces the area footprint by eliminating the need for dedicated test hardware, while testing capability is maintained through external scan sequence application to the scan chain latches.
Solution Approach 2:
The scan chain latches serve dual functions: they function as normal memory storage elements during regular operation and as testable components when scan mode is activated. This multi-functionality allows the same hardware to perform both storage and testing without requiring separate dedicated test circuits, thereby reducing area footprint while maintaining testing capability.
4Reliability
If multiplexers are used to control scan latches, then scan testing is enabled, but performance penalties occur
Solution Approach 1:
The patent removes the multiplexers from the SRAM structure entirely. Instead of using multiplexers to select between data inputs for scan latches, the design uses a scan chain where test data is shifted through consecutive latches using simple clock control, eliminating the performance penalties associated with multiplexer switching.
Data Source
AI summary
Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.