Scan Test Circuit Mode Selection for Delay Fault Coverage
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Solution Overview
Problem
Existing scan test circuits face challenges in reducing the number of delay fault test patterns while improving delay fault coverage, leading to increased area overhead when using extended scan flip-flops, which restricts design flexibility and increases costs.
Innovation Solution
A delay fault test pattern generation control circuit that selects between skewed-load and broadside modes based on a test pattern generation mode, using a test pattern generation mode control unit and scan enable signal output unit to optimize delay fault coverage without increasing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extended scan flip-flops are used to improve delay fault coverage and reduce the number of test patterns, then the delay fault coverage is improved, but the area overhead is increased
Solution Approach 1:
The patent applies dynamics by making the scan enable signal controllable and switchable between different modes (broadside and skewed-load) based on test requirements. The scan enable signal is generated dynamically by controlling the transition timing of scan flip-flops, allowing the system to adapt between different test patterns without permanent structural changes, thus improving delay fault coverage without increasing area overhead.
2Reliability
If the number of normal scan flip-flops to be replaced with extended scan flip-flops is increased to fully obtain the effects of improving delay fault coverage, then the delay fault coverage is improved, but the area overhead is increased
Solution Approach 1:
The patent applies universality by designing a multi-functional test circuit that can operate in both broadside and skewed-load modes using the same scan flip-flops. The scan enable signal controls the transition timing to achieve different test patterns from the same hardware resources, eliminating the need for separate extended scan flip-flops and reducing area overhead while maintaining improved delay fault coverage.
3Reliability
If skewed-load mode is used to reduce the number of test patterns and improve delay fault coverage, then the test quality is improved, but there are many restrictions in design
Solution Approach 1:
The patent applies dynamics by enabling dynamic switching between broadside and skewed-load modes through controllable scan enable signals. This allows the test circuit to adapt to different design requirements and fault conditions, providing both the benefits of skewed-load mode (reduced test patterns, improved coverage) and the flexibility of broadside mode when needed, thus resolving the design restriction issue.
Data Source
AI summary
To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.