IC Test Controller Skipping Redundant Patterns
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Solution Overview
Problem
The generation of pseudo-random test patterns for integrated circuits, such as microcontrollers, results in low test efficiency due to the inclusion of redundant patterns that do not contribute to test coverage, leading to wasted time and power consumption during testing.
Innovation Solution
A test arrangement that includes a test pattern generator and a controller to skip ineffective test patterns by using a memory to indicate which groups of test patterns should be used for testing, allowing only efficient patterns to be fed to the integrated circuit, thereby reducing unnecessary testing iterations and conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pseudo-random test patterns are generated and loaded into integrated circuit for testing, then test coverage is improved, but test efficiency deteriorates due to redundant patterns
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing effectiveness indications for groups of test patterns before actual testing. The controller checks these pre-stored indications to determine whether to execute test patterns, avoiding redundant testing. This pre-computation approach allows the system to maintain high test coverage while efficiently skipping ineffective patterns during execution.
2Reliability
If a high number of test patterns are generated to achieve high test coverage, then test coverage is improved, but testing time increases
Solution Approach 1:
The patent extracts and removes ineffective test patterns from the testing sequence by using pre-calculated effectiveness indications stored in memory. The controller selectively executes only those test patterns marked as effective, extracting the harmful element (redundant patterns) from the system. This extraction maintains comprehensive test coverage while significantly reducing the actual testing time by eliminating patterns that would not contribute to fault detection.
3Reliability
If redundant test patterns are executed, then test coverage is maintained, but power consumption increases
Solution Approach 1:
The patent implements feedback by using pre-calculated effectiveness indications that provide information about which test patterns are worthwhile to execute. The controller uses this feedback information to make informed decisions about pattern execution, avoiding redundant patterns that would consume power without adding test coverage. This feedback mechanism enables the system to maintain comprehensive testing while minimizing energy waste on ineffective patterns.
Data Source
AI summary
A test arrangement for testing an integrated circuit is described wherein the test arrangement comprises a test pattern generator configured to generate a sequence of test patterns, a memory storing an indication for each of a plurality of groups of one or more of the test patterns, whether to use the group of test patterns for testing an integrated circuit and a controller configured to, for each of the test patterns, control the test pattern generator to feed the test pattern to the integrated circuit if the test pattern belongs to a group that should be used for testing the integrated circuit and to skip the test pattern in the testing of the integrated circuit if the test pattern belongs to a group that should not be used for testing the integrated circuit.