Pulsed Flip-Flop Scan Test Circuit for Hold Time Violations
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Solution Overview
Problem
Conventional flip-flops in digital circuits face challenges in reliably testing logic states, particularly in high-performance modes where hold time violations occur, leading to errors and the need for additional design complexities to manage race immunity and signal delays.
Innovation Solution
A pulsed flip-flop design with integrated scan test functionality, incorporating a multiplexer and modified latch structures that allow operation as both a high-performance pulsed flip-flop and a conventional master-slave latch pair, enabling flexible mode operation to manage hold times and reduce race immunity risks without requiring separate scan clock trees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional master-slave flip-flop design is used for high-performance operation, then speed is improved, but hold time violations occur leading to reduced reliability
Solution Approach 1:
The patent implements dynamic operation mode selection where the flip-flop can switch between pulsed mode and master-slave mode based on operational requirements. The circuit includes mode control logic that dynamically reconfigures the internal transistor networks to adapt the hold time characteristics to the current operating conditions, thereby maintaining reliability across different speed requirements
Solution Approach 2:
The invention changes the operational parameters of the flip-flop by introducing a pulsed operation mode with adjustable pulse width and positioning. By modifying the clock signal parameters (pulse width, edge timing) and the corresponding transistor switching sequences, the circuit achieves extended hold time compliance while maintaining high-speed operation capabilities
2Adaptability or versatility
If separate scan clock trees are added to enable scan test functionality, then testing capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the scan test functionality with the existing clock distribution network by utilizing the same clock signal paths for both normal operation and scan test modes. The circuit incorporates mode control logic that redirects the same clock signals to different functional blocks (normal data path vs. scan path) based on operational mode, thereby enabling scan test capability without adding separate clock trees
Solution Approach 2:
The flip-flop design achieves multi-functionality by integrating both normal data storage/transfer operation and scan test operation within a single circuit structure. The same physical components (transistors, latches, clock inputs) serve dual purposes depending on the activation of control signals, eliminating the need for dedicated scan-specific hardware and reducing overall device complexity
3Reliability
If additional transistors and logic are added to manage race immunity and hold times, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic pulsed clock signals to control the switching sequences of the transistor networks. By using short, precisely-timed pulses instead of continuous clocking, the circuit achieves the necessary race immunity and hold time compliance only during the critical switching intervals, thereby reducing power consumption during stable state periods while maintaining reliability during transitions
Data Source
AI summary
A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.