Parallel Signature Unit for Hardware Data Integrity Verification
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Solution Overview
Problem
Conventional data integrity verification techniques for real-time and critical systems are either software-intensive or require significant additional hardware, leading to increased cost, complexity, and delay, which overburdens these systems.
Innovation Solution
An integrated data integrity verification technique using a processor with a parallel signature unit (PSU) that accumulates values from memory via a bus interface unit, allowing for hardware-based verification with flexible operation modes, including data integrity verification and pseudo random number generation, reducing overhead and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-intensive data integrity verification techniques are used, then verification capability is provided, but system delay and overhead increase
Solution Approach 1:
The patent replaces software-intensive verification techniques with a hardware-based parallel signature unit (PSU) that operates in parallel with the processor. This hardware implementation performs data integrity verification through parallel accumulation and comparison operations, eliminating the time-consuming sequential software processing while maintaining verification capability.
2Reliability
If conventional data integrity verification techniques are used, then verification is achieved, but hardware cost and complexity increase
Solution Approach 1:
The parallel signature unit (PSU) is designed to perform multiple functions: data integrity verification through accumulation and comparison, and pseudo-random number generation. This multi-functionality reduces overall system complexity by consolidating verification capabilities into a single integrated hardware module that serves multiple purposes within the processor architecture.
Solution Approach 2:
The patent merges the data integrity verification functionality directly into the processor architecture by integrating the PSU with the bus interface unit and memory system. This consolidation eliminates the need for separate verification hardware components, reducing overall system complexity while maintaining comprehensive verification coverage.
3Reliability
If conventional data integrity verification techniques are used, then verification capability is provided, but implementation cost increases
Solution Approach 1:
The patent combines data integrity verification functionality directly into the existing processor and memory interface architecture. By integrating the parallel signature unit with the bus interface unit and utilizing existing hardware resources, the implementation avoids the need for separate verification hardware components, thereby reducing manufacturing costs while maintaining comprehensive verification capability.
Data Source
AI summary
In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.