Semiconductor Memory Tester Frequency Division Timing
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Solution Overview
Problem
Conventional semiconductor memory testers face challenges in accurately testing high-speed DDR SDRAMs due to difficulties in maintaining the positional relationship of internally generated clocks and differential data strobes, leading to inefficiencies and potential false defect identification, especially at higher data rates.
Innovation Solution
A semiconductor memory tester with a measurement division that includes comparators, sampling units, fail detectors, and variable delay elements, which frequency-divides the clock output by the Device Under Test (DUT) to generate timing for comparison, allowing for efficient testing without complex program handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the tester uses a reference clock from the tester to set timing for input signals from the DUT, then the testing process is simple and straightforward, but the positional relationship between the internally generated high-speed clock and the reference clock cannot be accurately maintained, leading to potential false defect identification
Solution Approach 1:
The patent introduces a frequency dividing means as an intermediary component that divides the high-speed clock signal from the DUT to generate the reference timing signal for the tester. This mediator enables the tester to synchronize with the DUT's internal clock while maintaining operational simplicity, resolving the contradiction between ease of operation and measurement precision.
Solution Approach 2:
Instead of using the tester's reference clock to drive the DUT and set timing (conventional approach), the patent inverts the approach by using the DUT's internally generated high-speed clock as the basis for timing reference. The frequency dividing means divides this DUT clock to provide timing signals to the tester, thereby maintaining both simplicity and accuracy.
2Speed
If the tester uses a high-speed clock multiplied by PLL within the DUT to drive the interior of the DUT, then the data transfer rate is increased, but maintaining the positional relationship between this high-speed clock and the reference clock becomes difficult
Solution Approach 1:
The patent implements a feedback mechanism where the frequency dividing means continuously divides the DUT's high-speed clock to generate timing signals that are fed back to the tester. This feedback loop enables the tester to dynamically adjust and maintain accurate timing synchronization with the DUT's internal clock, preserving positional relationship stability even at high data transfer rates.
3Device complexity
If the tester conducts testing based on the assumption that the DUT operates in complete sync with the basic timing from the tester, then the testing program is simple, but this assumption breaks down at higher data rates where clock positional relationships cannot be maintained
Solution Approach 1:
The frequency dividing means serves as an intermediary that bridges the gap between the DUT's high-speed internal clock and the tester's timing requirements. By dividing the DUT clock to generate tester timing signals, it maintains testing program simplicity while ensuring testing accuracy even when the DUT operates at high data rates where synchronous operation cannot be assumed.
Data Source
AI summary
There is implemented a semiconductor memory tester capable of efficiently conducting a test on a fast memory by programming according to parameters of a device without being attended by complex program handling. The semiconductor memory tester for determining pass/fail on a memory device under test is characterized in comprising a measurement division for comparing an output from the memory device under test with an expected value at timing on the basis of a clock outputted by the memory device under test.