Programmable MBIST Controller for Flexible Memory Testing
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Solution Overview
Problem
Traditional built-in-self-test (BIST) controllers for memories in System-on-Chip (SoC) designs are non-programmable, limiting the ability to change test algorithms post-manufacturing, which can lead to reduced fault coverage and increased defect detection challenges as new fault models and algorithms are developed over time.
Innovation Solution
A programmable Memory BIST (MBIST) controller that supports linear and non-linear algorithms, allowing for the selection and application of new test algorithms at runtime, enabling flexible testing of memories at functional operating speeds and accommodating nested loops, with features like instruction memory, address generation, and diagnostic data recording.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional non-programmable BIST controllers are used, then device complexity is reduced and manufacturing is easier, but adaptability deteriorates as new fault models and test algorithms cannot be applied post-manufacturing
Solution Approach 1:
The BIST controller is designed with field-programmable capabilities, allowing its test algorithm behavior to be dynamically changed after manufacturing. The controller can be reconfigured to implement different test algorithms and fault models at various stages (manufacturing site or remote locations), transforming a static system into a dynamic one that adapts to new testing requirements.
Solution Approach 2:
The controller's operational parameters (test algorithms, fault models, testing sequences) are made changeable through field programming. This allows modification of the controller's behavior without physical redesign, enabling adaptation to new fault models and test algorithms while maintaining the same hardware structure.
2Reliability
If more test algorithms are developed post-manufacturing, then fault coverage is improved, but the ability to apply these algorithms deteriorates with non-programmable controllers
Solution Approach 1:
The controller is pre-designed with field-programmable capabilities built in during manufacturing, preparing the system in advance to accept and execute new test algorithms. This preliminary preparation ensures that when new fault models and algorithms are developed later, the controller is already equipped to implement them without requiring additional hardware modifications.
Solution Approach 2:
The BIST controller is designed as a universal platform capable of implementing multiple different test algorithms and fault models. Through field programming, a single controller can serve multiple functions by loading different algorithm sets, making it adaptable to various testing requirements and improving fault coverage across different defect types.
3Ease of operation
If Direct Memory Access (DMA) is used for testing, then test application is simpler, but silicon area and routing complexity increase
Solution Approach 1:
The BIST controller merges the test algorithm execution, address generation, data pattern generation, and result analysis functions into a single integrated unit within the memory chip. This consolidation eliminates the need for separate DMA controllers and associated routing, reducing silicon area while maintaining test application capability.
Solution Approach 2:
The memory system performs self-testing through the integrated BIST controller, which generates test patterns, applies them to the memory array, and analyzes results autonomously. This self-service capability eliminates the need for external DMA controllers to manage test operations, reducing both silicon area and routing complexity while preserving ease of test application.
Data Source
AI summary
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.