SoC Design Verification Using Virtual Model and Registers
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Solution Overview
Problem
The complexity of system on a chip design and the involvement of multiple designers make design verification challenging, with existing methods requiring extensive manual effort and lacking automation to ensure consistency between software and hardware parameters.
Innovation Solution
A system that uses verification programs executed by the processor to verify direct connections between circuit blocks without knowledge of their implementation, employing a circuit simulator to simulate system operation at different abstraction levels, and utilizing additional registers for observable access to connections, allowing for automated design verification without a physical prototype.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual verification methods are used to check consistency between software and hardware parameters, then verification can be performed with existing tools, but the verification effort and time consumption increase significantly
Solution Approach 1:
The patent creates a virtual model (copy) of the hardware system that mirrors the actual hardware parameters and structure. Verification programs execute on this virtual model to check consistency with software parameters, eliminating the need for manual verification while maintaining high reliability. The virtual model serves as an automated intermediary that can be queried and tested without physical hardware involvement.
2Manufacturing precision
If extensive manual verification is performed to detect design errors, then design accuracy can be maintained, but the complexity and effort of the verification process increase
Solution Approach 1:
The verification system is self-service in that it automatically performs consistency checks between software and hardware parameters without requiring manual intervention. The verification programs autonomously execute on the virtual model, compare results with software specifications, and identify discrepancies, thereby maintaining high design accuracy while reducing verification process complexity through automation.
3Measurement precision
If automated verification programs are executed on the actual system, then verification accuracy improves, but the system requires additional test circuitry that increases device complexity
Solution Approach 1:
The patent introduces a virtual model as an intermediary between the verification programs and the actual hardware system. This intermediary allows automated verification to be performed with high accuracy by simulating hardware behavior, while avoiding the need to modify the actual hardware with additional test circuitry. The virtual model absorbs the complexity of test infrastructure requirements.
4Reliability
If verification is performed before manufacturing, then design errors can be detected early, but the verification process becomes more critical and time-consuming
Solution Approach 1:
The patent performs verification actions preliminarily, before manufacturing, by executing verification programs on a virtual model of the hardware system. This preliminary verification detects design errors early in the design phase, preventing them from propagating to manufacturing. The automated nature of the virtual model verification maintains design process efficiency despite the critical importance of pre-manufacturing error detection.
Data Source
AI summary
A system on a chip comprises a plurality of circuit blocks, a programmable processor and a communication circuit. Design information includes connection data including an identification of the direct mutual connection and first and second circuit blocks coupled by the direct mutual connection. An additional register is added to the system on a chip coupled to the direct mutual connection. Verification programs are used includescomprising instructions for the processor to access registers in the second one of the circuit blocks, to use the connection data, or information derived therefrom to select the first one of the circuit blocks, and to issue the standardized call to the interface program of the selected further one of the circuit blocks.