In-die Transistor Characterization via Integrated DAC and ADC
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Solution Overview
Problem
Current wafer acceptance testing (WAT) techniques cannot effectively test integrated circuit (IC) characteristics once the ICs are separated from the wafer, and they are limited in their ability to provide detailed transistor characterization, especially after sorting and packaging.
Innovation Solution
In-die transistor characterization is achieved by integrating digital-to-analog (DAC) and analog-to-digital (ADC) converters within the IC to drive and measure voltage signals across transistors, allowing for the derivation of electrostatic characteristics such as current-voltage relationships and threshold voltages directly on the IC die, either independently or while still on a wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test structures are disposed in peripheral regions of the wafer (within scribe lines), then testing can be performed on the wafer prior to sorting and packaging, but the test structures do not directly test characteristics of the ICs themselves and cannot be used to test ICs once separated from the wafer
Solution Approach 1:
The patent divides the testing function into two segments: wafer-level testing using peripheral test structures, and post-separation testing using in-die test circuits integrated within each IC. This segmentation allows each testing method to serve its specific purpose - WAT for initial quality control and in-die testing for continued characterization after sorting and packaging
Solution Approach 2:
The patent embeds test circuits and transistor modules directly within the IC die area, nesting the testing functionality inside the product itself. This allows the IC to contain its own testing capability, enabling continued characterization after separation from the wafer without requiring external test equipment
2Productivity
If a limited number of test structures are formed on the wafer, then testing time during manufacture is reduced, but detailed transistor characterization of individual ICs cannot be achieved
Solution Approach 1:
The patent segments the transistor population into many individual transistors distributed across the IC die, with each transistor accessible for separate characterization. This allows detailed measurement of individual transistor properties without requiring a large number of shared test structures, achieving both speed and precision
Solution Approach 2:
Each IC contains its own in-die test circuits and transistor modules that can be self-tested without requiring external test equipment or additional wafer-level infrastructure. This self-service capability enables detailed characterization to be performed quickly using the IC's own resources
3Ease of manufacture
If traditional WAT techniques are used, then wafer-level testing can be performed, but IC-level testing after sorting and packaging becomes impossible
Solution Approach 1:
The patent implements test circuits with universal functionality that can operate in multiple contexts: during wafer-level testing and after IC separation and packaging. The in-die transistor modules and control circuits are designed to be universally applicable across different testing scenarios and time points in the manufacturing and usage lifecycle
Solution Approach 2:
The patent incorporates test circuits and transistor modules into the IC during the initial fabrication process, performing the setup for future testing in advance. This preliminary action ensures that the testing capability is built-in before sorting and packaging, enabling continued characterization throughout the IC's lifecycle including field use
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables comprehensive transistor characterization across the IC die, accounting for die-variation, and allows testing at any time, including after IC-level tests or in-field use, without requiring dedicated test interfaces or supplies, thus overcoming the limitations of traditional WAT.
Implementation Method 1
a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input
Implementation Method 2
an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors
Implementation Method 3
the samples being indicative of at least one electrostatic characteristic for the plurality of transistors
Data Source
AI summary
In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.