Voltage-Controlled Delay Comparator for Shorter ADC Decision Time
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Solution Overview
Problem
Conventional high-speed analog-to-digital converters (ADCs) are slowed by comparators that require input signals to be held for a long time, introducing timing complexities and reducing the speed of the ADC due to the time it takes for the comparator to make a decision, typically greater than 100 ps in 65 nm technology.
Innovation Solution
A high-speed latch comparator is developed, incorporating a voltage-controlled delay circuit that converts input voltage information into time information, allowing the input clock to be delayed proportionally to the input voltage, reducing the decision time to approximately 25 ps and eliminating the need for holding input information during the comparison process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional comparators are used in high-speed ADCs, then the comparison function is achieved, but the decision time exceeds 100 ps which slows down the ADC speed
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitors in the delay circuit to specific voltage levels before the comparison operation. This pre-positioning of energy states allows the comparator to make decisions much faster (approximately 25 ps) because the circuit is already prepared with the necessary charge states, eliminating the need for slow charging/discharging during the actual comparison.
Solution Approach 2:
The patent implements dynamics by using voltage-controlled delay circuits that dynamically adjust the timing of clock signals based on the input voltage levels. The delay amount is proportional to the input voltage, creating a dynamic timing mechanism that adapts to different signal conditions and enables faster decision-making compared to static comparator designs.
2Reliability
If conventional comparators hold input signals for long time, then the comparison can be completed, but timing complexities are introduced
Solution Approach 1:
The patent replaces the mechanical/time-based holding mechanism with a voltage-controlled delay mechanism. Instead of holding input signals for fixed long periods, the system uses voltage-proportional delays where the timing is dynamically determined by the signal levels themselves, simplifying the timing control while maintaining reliable comparison results.
3Productivity
If conventional comparators are used, then the comparison function is achieved, but the decision time of approximately 100 ps reduces productivity
Solution Approach 1:
By pre-charging capacitors to specific voltage levels before comparison, the circuit is prepared in advance with the necessary energy states, reducing the actual decision time from over 100 ps to approximately 25 ps and thereby increasing ADC productivity.
Solution Approach 2:
The patent changes the timing parameter dynamically based on voltage levels. The delay amount is proportional to the input voltage, allowing the system to optimize comparison speed for different signal conditions and achieve faster overall operation compared to fixed-timing comparators.
Data Source
AI summary
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.