Analogue/Digital Conversion TRIZ Cases

Polarity inversion in a triangular-wave PWM quantizer compensates speaker-voltage mode changes to keep combined gain stable and reduce ramp swing variation.

Pre-charged reference capacitors equalize loading in a single-ended gain stage, reducing common-mode offset and mismatch-driven ADC nonlinearity.

PWM time encoding multiplies analog signals through frequency-based counting, cutting power and heat while avoiding drift and mismatch.

A single switched current path compares one input against multiple thresholds, improving accuracy while cutting replica circuitry, power use, and parts.

A DPDT reference-switching multiplexer cuts ECG channel switching noise before ADC conversion, improving signal clarity and measurement accuracy.

A delta-sigma modulator and staged digital filtering improve converter output current timing resolution for tighter control-loop synchronization.

A modulated clock carries configuration across an isolation barrier, preserving sensor data accuracy under harsh electrical conditions.

Dual measurement circuits time-interleave sensing and calibration to cut inductive encoder latency while improving accuracy for fast motion.

Calibrated pulse mapping corrects undersampling errors in scintillation energy measurement, improving digital radiation detection accuracy.

Clock-signal modulation carries control data across an electrical barrier, improving long-distance measurement accuracy and noise robustness.

Parallel filters and undersampled ADCs capture high-frequency signals at lower sampling rates while avoiding phase-offset compensation.

Separate DSP paths let one channel trigger on IQ signal characteristics while another acquires data with independent parameters at lower cost.

A coarse flash ADC updates modulator references through a feedback DAC to cut quantization noise, power use, and support multi-mode RF.

Low- and high-temperature compensation circuits trim analog offset drift at different rates while preserving continuous signal output.

Non-linear chaotic iterations turn tiny input differences into detectable divergence, improving signal-change resolution despite noise and ADC cost.

An anti-aliasing filter and comb filter clean touch-panel sensing signals before ADC conversion, improving signal quality with less circuit area.

Complex CIR estimates, preamble correlation, and matched filtering improve UWB timing and carrier recovery under multipath noise with lower power.

Periodic capacitor switching creates notches at sampling-frequency multiples, suppressing aliasing while improving filter linearity and dynamic range.

A separate high-swing buffer drives the pass transistor gate to improve track-and-hold linearity and cut charge injection without bootstrap circuits.

An opposite phase-variation amplifier offsets divider drift with temperature, keeping multi-frequency clocks synchronized for stable AD conversion.

Negative feedback keeps node signals aligned between reset and integration stages, cutting 1/f noise and output jump as counts rise.

Two ADCs sample a loop-filter output at different times to extend bit-cycling time and cut quantization noise in CT delta-sigma modulators.

Time-interleaved sigma-delta modulation and DEM reduce mismatch errors, widening SDR transmitter bandwidth without extreme clock rates.

A feedback-loop TEM uses a comparator, latch, and digital delay to cut power and size while keeping time-encoded signal transitions synchronized.

Splitting an RF input into parallel delta-sigma paths eases multi-GHz switching limits while preserving linearity and PA efficiency.

Pulse-amplitude modulation combines multiple memory bitstreams into one multilevel shared-bus signal to overcome I/O throughput limits.

One transducer feeds two signal-conditioning paths to keep pressure sensing accurate across narrow and wide ranges with lower cost and tubing complexity.

A DPDT switch precharges each multiplexed ECG channel to a reference voltage, cutting switching noise and preserving fast ADC settling.

Extra switches and sampling capacitors double differential hold voltage, improving ADC signal-to-noise ratio with adjustable amplification.

Parallel IQ down-conversion and misalignment equalizers suppress ADC spurs with fewer multipliers, enabling real-time baseband processing.

Parallel quantizers with analog differential dither cut ADC spurs and improve SFDR while keeping the noise floor low.

Input voltage is converted into clock delay so a latch comparator can decide in about 25 ps without long input holding in high-speed ADCs.

A diplexer and wideband ADC combine signals across Nyquist zones with minimal insertion loss, preserving accuracy in BER testing.

Clock-synchronized hysteretic modulation cuts ADC power use while preserving noise shaping and accurate time-encoded conversion.

Phase-offset shifting approximates RF signals within quantized intervals, cutting out-of-band noise, spurs, and DTC power use.