Interleaved CT Delta-Sigma Quantizer for Longer Bit-Cycling Time
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Solution Overview
Problem
In continuous-time delta-sigma modulators, the excess loop delay restricts the decision time for bit cycling, leading to wasted sampling period and increased quantization noise due to the requirement for wider bandwidth and faster sampling rates.
Innovation Solution
Implementing a continuous-time delta-sigma modulator with multiple ADCs sampling the filtered signal at different times, allowing for the generation of output signal components at distinct times within the sampling period, thereby fully utilizing the sampling period and reducing quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the excess loop delay is reduced to less than one sampling period (e.g., 0.5*Ts), then the CTDSM loop stability is maintained, but the decision time for bit cycling is restricted and the remaining sampling period is wasted
Solution Approach 1:
The patent divides the single quantization decision process into multiple stages by introducing a first quantizer and a second quantizer. The first quantizer performs initial quantization within the ELD period, while the second quantizer performs additional quantization in the remaining sampling period. This segmentation allows the system to maintain loop stability with limited delay while fully utilizing the entire sampling period for quantization decisions.
Solution Approach 2:
The first quantizer performs preliminary quantization of the filtered signal within the excess loop delay period, generating an intermediate quantization result. This preliminary action allows the feedback path to remain stable while the second quantizer continues to refine the quantization decision using the remaining sampling time, thus preventing wasted time while maintaining reliability.
2Productivity
If the sampling rate is increased to achieve wider bandwidth, then the CTDSM bandwidth requirement is met, but the decision time for bit cycling becomes insufficient
Solution Approach 1:
The patent ensures continuous utilization of the sampling period by implementing two quantizers that operate sequentially. The first quantizer operates during the ELD period and the second quantizer operates during the remaining period, eliminating idle time and ensuring that the increased sampling rate is fully exploited for productive quantization decisions rather than being constrained by insufficient decision time.
Solution Approach 2:
By segmenting the quantization process into two distinct stages with two separate quantizers, the system can maintain high sampling rates while providing sufficient decision time for each quantization stage. The first quantizer handles the urgent quantization within ELD, and the second quantizer refines the decision, ensuring that bit cycling has adequate time even at higher sampling rates.
Data Source
AI summary
The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.